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October 10, 2005
DIAMOND in the Rough?
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


On September 17, 2005 EverCAD Corporation, a private EDA firm specializing in advanced circuit simulation & analysis tool suite for analog, mixed signal, and SOC designs, announced the availability of its new DIAMOND product line. DIAMOND stands for Digital Analog Macro-oriented verification ONDemand. DIAMOND is a state-of-art mixed-signal verification tool for the comprehensive verification of full-chip mixed-signal system-on-chip (SoC) designs. EverCAD has appeared at the several industry tradeshows such as DAC and the Embedded Systems, EDA & Test Conference. However the newsroom section of its own website does not list anything since last November, not even the DIAMOND announcement.
Web searches reveal little.

I had a chance to speak with Dr. Pole Shang Lin, CEO and President of EverCAD Navigator Company. The material below is based upon that conversation and various written materials provided by the firm.

Dr. Lin received the B.S. and Ph.D. Degrees in electrical engineering from the National Chiao-Tung University, Republic of China. After teaching electronics at the Chinese Army Communication School, he entered the Electronic Research and Service Organization, the Industrial Technology Research Institute. He led the section project of TCAD in submicron project and engaged in the research and development of semiconductor device modeling. This later became a part of Vanguard. He then became Director of TCAD at Silicon-Based Technology Corp. In 1998, he joined the EverCAD Software Corp. as the general manager and the project leader. In 2001, he became CEO of EverCAD Navigator Corp., the
US subsidiary of EverCAD Software Corp.

EverCAD was founded in 1998. It is a private, self-funded company. The firm has 20 people overall split between Fremont, California and the Science-Based Industrial Park in Hsin-Chu, Taiwan, R.O.C. The installed base consists of approximately 70 customers with over 200 licenses sold. The customers are in the US and in Asia. Among these customers are UMC, Cisco, LSI Logic, MediaTek, Chartered Semi, Mstar Semiconductor, InProComm, Faraday Technology, SiS, Archband Labs and Silicon Bridge.

The company sells direct in the US and Taiwan and through distributors in Korea and Japan. EverCAD has no customers as yet in mainland China. Protection of intellectual property rights is a concern in that country.

ADiT-Turbo is an all-in-one advanced circuit simulation tool suite for full chip and SoC designs in analog, mixed mode, and multi-level environment. It features revolutionary single engine architecture, coupled with a superior set of user-friendly, accuracy, speed and performance. With partition algorithm and simplified matrix solver, ADiT-Turbo can simulate large circuit with simulation speed 10X~ 100X faster than that of SPICE.
ADiT-Spice is an advanced SPICE solver with charge conservation model and non-quasi static effect designed to yield supreme accuracy. ADiT-Spice uses built-in table-look-up MOSFET model designed to result in > 3X faster speed while keeping close-to-SPICE accuracy.

ADiT-MOT is a macro-oriented technology used for full-chip circuit simulation, e.g. DRAM, SRAM, flash, CAM andLCD drive. ADiT-MOT will verify your design with 100X to 1000X faster than that of SPICE with analog accuracy and quality. With ADiT-MOT's high-speed MOT algorithm, Giga-size transistor-level simulations are possible.

ADiT-HDL is a HDL solver that has been specifically designed for SoC and mixed-signal designs. Because it is based on single-kernel technology with ADiT-Turbo and ADiT-MOT, the mixed-signal simulation result is very accurate.

ADiT-VPI (Verilog Procedural Interface) supports seamless integration of ADiT simulator with VCS, NCVerilog, Verilog-XL and ModelSim. Users are allowed to specify the D/A and A/D interfaces with ease and it is perfect solution for SoC designs.

AView is designed to be a simple and intuitive interactive post-simulation analysis tool. Analog, digital and mixed-signal engineers can now use same waveform analyzer to analyze analog/digital signals in a single tool.

ADiT-FLI (Foreign Language Interface) combines the powerful electrical engines of ADiT-SPICE, ADiT-Turbo, and ADiT-MOT, for SPICE design, with ModelSim's VHDL simulator.

ADiT-AMS: High Performance High Capacity Mixed Language (e.g. SPICE, Verilog, VHDL, Verilog-AMS) Simulator.
EverCAD offers ADiT in an OEM package, although Dr. Lin would not identify any current customers.

DIAMOND is designed for circuit level verification of designs with more than a million gates, including mixed-signal, SoCs, video and network processors, DSPs' Flash, SRAM, DRAM, CAM and other memory like structures. DIAMOND's inherent strength is in its ability to accurately simulate Delta-sigma, ADC/DAC, switched-capacitor filters, PLLs, charge pumps, high-speed transceivers and large analog designs which require long simulation times when using SPICE tools.

With DIAMOND EverCAD is targeting three areas. 1) Top-Down designs which need detailed timing and power verification. 2) RAM-compiler users. 3) Complex mixed-signal SoC design engineers.

DIAMOND will be available on all major platforms including Solaris, HP-UX, Windows, and RedHat Linux including Red Hat Enterprise Edition.

Pricing for DIAMOND is around $150K. ADiT pricing was $100K to $130K depending upon the modules licensed.

Dr. Lin says that EverCAD target markets are high speed IO, power management, high-resolution AD/DA, and mixed-signal SOC design. He identified Nassda as the firm's principal competition and claimed that EverCAD provides a more accurate solution.

He believes that the major problem is interface and that interface is a purely artificial element. He believes that this is an important issue for customers and that EverCAd has solved the problem. The current approach for mixed signals between analog and digital blocks are through two A2D and D2A behavior devices. The user needs to specify some parameters such delay-time, rising-time, falling-time, driving resistance before simulation. This may cause accuracy problem for some high-speed design. DIAMONDS creates this automatically.

The product can be used for simulating small blocks during the design phase and at tapeout for full chip verification: function, timing and power.

Diamond provides a complete functional, timing and power analysis solution for analog mix signal designs verification. Our solution not only provides an easy of use environment, but also with performance and accuracy.

In particular Dr. Lin pointed to a customer success story based on Archband Labs's mixed signal design of 24bit delta sigma audio ADC with clock generator and DSP. Without using behavior models, designers can perform full-chip simulation by combining SPICE and Verilog parts together for more reliable and accurate verification. Previously analog and digital designers verified only their own piece of the design.

EverCAD has two beta sites for DIAMONDS and expects the product to be available the end of this quarter.

On the litigation front Synopsys filed two additional suits against Magma on September 26. We had covered the original suit in considerable detail in our June Editorial, entitled
Magma-Synopsys Litigation. One of the new suits is a claim of unfair competition against Magma based upon Magma's action in defending itself in the patent case, while the other deals with additional patent infringement. At least one of the patents in questions comes from Synopsys' acquisition of Monterey Design Systems.

In a September 28 press release Magma President and Chief Operating Officer Roy E. Jewell said “These actions are questionable, perhaps laughable, and indicative of an increasingly desperate strategy by Synopsys to maintain market share. They likely concluded that their current case is weak - because of validity and ownership issues, to name just two - and so are attempting to bolster it by piling on these dubious claims. We're truly disappointed to see these latest actions by Synopsys, given that the industry already suffers from a reputation for excessive litigation. He added “Candidly, I am troubled that a company that was once the leader in our industry has resorted to
these egregious tactics to defend a declining market position against an up-and-coming innovator like Magma. I can only hope this strategy is the result of a legal team out of control. “

At the center of this litigation are the actions of a key Magma employee that had previously worked at Synopsys. As discussed in the earlier article an individual's attractiveness to potential employers is often a function of specific experience and knowledge rather than IQ or general technical acumen. It is often difficult to separate out proprietary material of a current or former employer from an individual's knowledge. Employer sometimes use non-compete clauses in employment contracts to protect their trade secrets. These can be difficult to enforce particularly in California unless there is some form of compensation to the employee. Most non-compete clauses also contain
provisions to prevent recruiting of current employees by former employees. A firm hiring someone from a competitor should in their own best interests remind new hires of their obligations to past employers. Some companies may try to erect a Chinese wall to isolate the new hire from projects related to prior employment. Some firms in their efforts to protect their intellectual property take legal action to prevent former employees from joining the competition or restricting their activities once the have joined.

A recently highly publicized example is the case of Kai-Fu Lee. Lee joined Washington State-based Microsoft in 2000. He helped established MS research center in Beijing, In July 2005 Lee joined Google in July to lead the California-based Internet search engine company's expansion into China. He was to oversee a research and development center that Google plans to open in China Microsoft sued Google and Lee, who is known for his work on computer recognition of language, a key problem in search technology. Microsoft contends that Lee's duties would violate the terms of a non-compete agreement he signed as part of his Microsoft employment contract. Microsoft also accused Lee of using insider information to get his job at Google. MS attorneys have made a lot of an email that Lee sent to Google executive stating “I am currently the corporate vice president at Microsoft working on areas very related to Google”. MS alleged that Lee sent confidential documents about the company's China strategy to Google a month before he was hired, although Google insists all the material that Lee relayed to Google had been made public previously. MS further alleges that before resigning from Microsoft, Lee began to help Google plot its China strategy with a series of suggestions, including recommending possible sites for the new office. Google countersued to
invalidate the MS employment contract. Incidentally, Washington Sate law allows for enforcement of “reasonable” employment contracts.

Among the nuggets emerging from this case is allegation that MS CEO Steve Ballmer vowed to "kill" internet search leader Google in an obscenity-laced tirade during an exit interview with a software engineers who was resigning to join Google. Balmar says that this characterization of that meeting is not accurate. Lee says that he was threatened with a lawsuit in meetings with Gates and Balmar.

According to court documents Google paid Lee a $2.5 million signing bonus and promised a $1.5 million bonus after one year, plus a $250,000 salary and options on 10,000 shares of Google stock.

In mid September a judge ruled that Lee could begin working for Google in China immediately, but with limitations. According to his ruling Lee can not be involved in anything technical at Google for at least the next four months, and he can't have any budgetary or hiring authority during that period. However, he can use his knowledge of China's business community and his contacts in China's government and universities to help Google find the best space for its operations and to recruit engineers. He can also give promotional speeches about Google in China. Lee is barred from hiring anyone away from Microsoft and from using confidential information he learned during his employment there.
A trial is schedule for January. Stay tuned.

The top five articles over the last two weeks as determined by the number of readers were:

Technologies, Inc., a leader in yield management software and test chip solutions. IN an all cash transaction Synopsys will acquire HPL for approximately $13 million, or $0.30 per share. The transaction will require HPL shareholder approval. It is expected to close during Synopsys' first quarter of fiscal 2006 and is subject to customary closing conditions.

IEEE approves property language standard The new standard, IEEE 1850, “Standard for PSL: Property Specification Language,” specifies the design behavior of electronic systems using properties, assertions and other approaches. It was developed within the IEEE Standard Association's Corporate Program. IEEE 1850 refines the Accellera PSL 1.1 specification which provides for property-based verification

Samsung Electronics to invest $33 billion in semiconductor manufacturing facilities This is the second round of investments in its Hwaseong semiconductor plant. As part of the company's seven-year investment plan for the site. Hwaseong's second phase will be located on 230-acres that is slated to house one R&D facility and eight fabrication lines by 2012, calling for an estimated capital expenditure of $33 billion.

EDA Industry Reports Flat Revenue in 2nd Quarter of 2005 EDA Consortium's Market Statistics Service announced that EDA industry revenue for Q2 of 2005 was $1,091 million, versus $1,094 million in Q2 2004. Total product revenues, without services, were $1,028 million in Q2 of 2005 vs. $1024 million in the same quarter of 2004.

Cadence Announces New Capabilities to Simplify and Accelerate PowerPC Design; Custom-Synthesized Design Approach Reduces Time to Market for PowerPC Designers The new approach results in up to a 30 percent increase in processor speed and a 40 percent reduction in chip area. Developed in close collaboration with IBM, the custom-synthesized approach provides a new schedule-performance tradeoff point for performance-minded SoC designers embedding PowerPC cores.

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-- Jack Horgan, EDACafe.com Contributing Editor.