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July 15, 2002
EDA Week in Review
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Ann Steffora - Contributing Editor

by Ann Steffora - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

EDA Veteran Paul Lippe Returns as President and CEO of InTime Software;

NASDAQ Halts Trading of HPLA, Chairman and CEO MIA

Topping the news this week was the appointment of Paul Lippe to president and CEO of InTime Software, Inc. Lippe was formerly senior vice president of business and market development at Synopsys, Inc. After departing from Synopsys in October 1999, Lippe served as CEO of SKOLAR, spun out of Stanford Medical School that developed e-learning and digital library technology.
Lippe said coming back to EDA after delving into the Internet realm gave him a "re-recognition of the fundamental value of EDA. It's key technology to drive a whole society forward," he explained.
In other news, this on the not-so-pleasant side, the Nasdaq Stock Market halted trading of silicon infrastructure player HPL Technologies, Inc. for "additional information requested." The company has since blamed the mishap on its former chairman and CEO David Lepejian who cannot be located, the company reported. Nasdaq said trading in the security would remain halted until the company has fully satisfied its request. Earlier, HPL Technologies did report that it began investigating certain accounting irregularities involving revenue reported during prior periods, removed Lepejian. Based on a preliminary investigation, the company said it appears that a material amount of revenue was
improperly recognized during one or more earlier periods from sales to an international distributor.
Positive news did come out of the silicon infrastructure space, with PDF Solutions, Inc.'s announcement that it has expanded its yield simulation and analysis capabilities in Yield Ramp Simulator (YRS) 3.0 software, to be released in August. The new version of the company's software strengthens its proprietary approach to predict, analyze, and improve yield of ICs, the company said.
YRS software is a yield modeling and analysis tool that evaluates the impact of specific IC design attributes and manufacturing process variations. Version 3.0 offers an order of magnitude throughput improvement, increasing the amount of data that can be analyzed accurately in the same time period, PDF said. The latest version also provides a more flexible design attribute extraction engine, which enables fast and accurate analysis of process-design interactions, especially suited for today's largest, most complex designs, the company explained. The new features of the software continue PDF's strategy toward Design-Based Yield Improvement technology.
LogicVision, Inc. formed an engineering support and services division for engineering and consulting services for chip, board and system level design-for-test (DFT). In addition, LogicVision appointed Kenji Baba to vice president of the new division. Baba is chartered with the management and expansion of the division's focus on supporting customers' seamless implementation of Embedded Test from chip design through to systems development.
LogicVision believes the new division will provide its customers with additional LogicVision resource to help shorten implementation time, as well as foster seamless hand-off of chip design integration to manufacturing test. The engineering and consulting services will play a vital role not only in enabling the accessibility of LogicVision's proven Embedded Test Solution, but also in optimizing for future chip design and manufacturing applications, the company said.
LogicVision said it's engineering service and support division will focus on five major activities that include: (1) test architecture consulting services; (2) turnkey DFT services; (3) test program generation; (4) debug and test services; and (5) worldwide applications engineering support.
LogicVision also announced that Trebia Networks, Inc. successfully implemented LogicVision's Embedded Test Solution for silicon debug in its prototype storage networking chip. Based on this experience, Trebia said it plans to leverage LogicVision's Embedded Test technology for its follow-on chip scheduled for production. With the prototype chip, Trebia said it has already seen dramatic improvements over traditional test methods as measured by reduced time-to-debug (from hours to weeks) and reduced cost.
LogicVision's Embedded Test technology was applied on Trebia's 0.18-micron prototype chip to isolate initial test program issues. Trebia ran multiple tests on its device in a lab setup environment within minutes, the companies reported.
Thirdly from LogicVision, the company said that Teradyne production testers Catalyst and Tiger are certified by LogicVision to be Embedded Test Ready, which means they are able to access LogicVision's Embedded Test Solution. This integration is a result of a continued partnership between the two companies, and provides mutual customers with an optimized test solution designed to speed time-to-volume production and reduce total cost of test, the companies said.
Accelerated Technology, the Embedded Systems Division of Mentor Graphics Corp. revealed that the code/lab Embedded Developer Suite for MIPS-based processors is now available. This code/lab release supports the MIPS architectures and MIPS-based processors developed by MIPS Technologies' licensees such as IDT, NEC Corporation and QuickLogic. The addition of code/lab broadens the Accelerated Technology Real-Time Operating System (RTOS) offering to developers building high-performance, low-power system-on-a-chip (SOC) applications.
Cadence Design Systems, Inc. said that Sean M. Maloney, executive vice president of Intel Corp. and general manager of the Intel Communications Group, has been elected to the Cadence Board of Directors. Maloney, an Intel employee since 1982, has held a number of technical, managerial and executive posts in Europe, Asia and the United States. He is also a member of the Board of the US/China Business Council.
Synopsys, Inc. has hired intellectual property (IP) expert Pierre Bricaud as director of research and development for its Intellectual Property and Systems business unit. His responsibilities include driving the company's growing IP business in Europe and working closely with European customers to ensure that Synopsys' IP solutions solve their design challenges. Bricaud comes to Synopsys from Mentor Graphics where he started Mentor's IP Factory in Sophia Antipolis, France in 1997. Later he became responsible for SoC European strategic relationships. He holds an engineering degree from the Institut Superieur d'Electronique de Paris (ISEP) with a major in computer science.
Additionally, Bricaud and Michael Keating, vice president of engineering of Synopsys' IP and Systems business unit, recently published the third edition of Reuse Methodology Manual for System-On-A-Chip Designs, available from Kluwer Academic Publishers.
Open Core Protocol International Partnership (OCP-IP) announced that Mentor Graphics' Inventra IP Division has joined the organization. Membership in OCP-IP enables Mentor to provide its customers better design reuse and faster time-to-market by ensuring the rapid creation of interoperable virtual components.
Virtual Silicon Technology, Inc. received an order from 1st Silicon, Malaysia's largest wafer foundry, to port its SIP to 1st Silicon's 0.18-micron process technology. The agreement covers Virtual Silicon's standard cell library as well as two I/O pad libraries.
Q Design Automation announced that Artisan Components has completed an agreement to license Q Design's Qtrek-Migrate IC layout optimization software. Artisan said it would use the software as part of its automated flow to migrate standard-cells, memories, and memory compiler products to next generation processes.
Sunplus of Taiwan said it has deployed Conformal Logic Equivalence Checker (LEC) from Verplex Systems, Inc. throughout its IC design flow. In addition, Sunplus said it is using Conformal LEC as its final standard sign-off criteria for all of its chip designs.

Altera Corp. said the U.S. District Court for the Northern District of California issued a preliminary injunction enjoining Clear Logic, Inc. and its distributors from selling semiconductor devices made, designed, configured or programmed through or with the aid of Max+PlusII software-generated bitstream files. Altera also said the court ordered Clear Logic to destroy all semiconductor devices in their possession that were programmed with the output of Altera's software tools.
Clear Logic had previously disputed Altera's contentions. Clear Logic filed for bankruptcy protection under Chapter 11 of U.S. bankruptcy law in January 2002. The company's filing was prompted, in large part, by the pending Altera litigation. Altera sued Clear Logic in November 1999, alleging interference with customer relations and unlawful appropriation of registered mask work technology. In October 2001, the court issued several rulings including a finding that as a matter of law using the bit stream from Max+PlusII to program Clear Logic devices violates Altera's software license.
Altera released version 2.1 of the Quartus II design software, featuring a new timing closure methodology based on ASIC design techniques that can significantly accelerate the process of meeting timing requirements in multi-million gate system-on-a-programmable-chip (SOPC) designs. Altera said it is the first programmable logic supplier to deliver a methodology for timing closure as an integrated part of its existing tool suite. One of the significant new features of Quartus II version 2.1 is the new SignalTap II embedded logic analyzer. Altera said its SignalTap II is a second-generation system-level debug tool that captures and displays real-time signal behavior in SOPC
Fourth from Altera was a new, faster speed grade for its Stratix devices. The company said that a combination of process technology improvements and software algorithm options has yielded up to an additional 20 percent performance in the Stratix family. This increase brings the total overall performance improvement over previous Altera devices to an average of 60 percent or more since the Stratix devices were announced in early 2002.
Altera's fifth announcement of the week was its unveiling of a 12.8 Gbps HyperTransport technology running on a Stratix EP1S25 device at the Platform Conference in San Jose. In addition, as well as a HyperTransport IP core that supports version 1.03. The new MegaCore function supports the complete HyperTransport protocol and is fully compliant with versions 1.03 and 1.01a of the HyperTransport specification. The MegaCore function is parameterizable with programmable configuration space, variable buffer sizes and supports Altera's Atlantic on-chip bus interface. The HyperTransport MegaCore function consumes 10,000 logic elements in a Stratix device and is shipping to customers today.
HyperTransport interfaces are currently available on a wide range of devices, including network processors, co-processors, video chipsets, and ASICs.
Actel Corp. said its FPGAs were chosen by the German Aerospace Center (DLR) for its Bi-Spectral Infrared Detection (BIRD) satellite, that uses infrared sensor technology to detect and investigate high-temperature events on Earth, such as forest fires, volcanic activities, burning oil wells and coal seams. More than 20 Actel high-reliability FPGAs are used in many mission-critical functions on the satellite, including payload data handling, memory management, interfacing and control and co-processing as well as sensor control in the infrared camera.
Magma Design Automation, Inc. joined the Fabless Semiconductor Association and will be represented on two of the organization's committees. Rajeev Madhavan, Magma's chairman and CEO, will become a member of FSA's CEO Leadership Council, which provides the FSA with strategic leadership and direction to move the organization to its next level of success. Nitin Deo, vice president, business development at Magma, will participate in FSA's Intellectual Property Subcommittee. The objective of the IP Subcommittee is to address the many challenges in the portability, reuse, verification, integration and standardization of intellectual property in the semiconductor industry,
particularly as it applies to fabless companies and their partners.
Mentor Graphics Corp. announced that Matsushita Electronic Components Co., Ltd. (MACO) would now offer AutoActive technology for the MACO PCB ALIVH (Printed Circuit Board Any Layer Interstitial Via Hole) design kit for Mentor Graphics Expedition PCB, Board Station RE and SFX RE users. ALIVH is the PCB technology that makes it possible to decrease the size of cellular phones. Mentor Graphics and MACO jointly endorse AutoActive as the industry standard PCB layout technology that enables ALIVH to improve the productivity of their mutual customers. Through Mentor's OpenDoor program, MACO now has qualified Mentor products using AutoActive technology to support and test its advanced
ALIVH manufacturing process.
The RapidIO Trade Association announced new members have joined the open-standard interconnect organization, including Cypress Semiconductor Corp., Integrated Device Technology, Inc., National Semiconductor Corp., PMC-Sierra, STMicroelectronics, Cadence Design Systems, Inc., Synopsys, Inc., OSE Systems, Inc., IC4IC and Leopard Logic, further expanding the infrastructure for the open-standard, switch-fabric interconnect.
The RapidIO interconnect architecture addresses the need for reliability, increased bandwidth, and IP reuse for the rapid assembly of communication systems. This packet-switched, high-performance interconnect technology is designed to be compatible with most integrated communications processors, host processors, and networking digital signal processors. According to the RapidIO Trade Association, the standard enables chip-to-chip and board-to-board communications at speeds of ten Gigabits per second and beyond, while maintaining embedded software compatibility with older PCI-based systems at a fraction of the previous pin count.
In related news, Cadence announced a verification design kit meant to enable systems integrators to design and verify their communications systems faster by implementing the RapidIO standard for high-speed interconnect. This kit includes Cadence EDA technology, services to apply the technology to specific customer needs, and integration with IP from Motorola, Inc., the company explained. This kit is part of the Cadence Design Chain Initiative, which helps companies tighten development relationships throughout their design chain, optimizing the chain. Incorporating verification information related to Motorola's IP into Cadence standard verification offerings enables joint
customers to design-in Motorola's IP more quickly and effectively.
In more RapidIO-related news, Leopard Logic, Inc. announced a RapidIO platform based on its HyperBlox embedded FPGA cores. The platform supports the RapidIO 1x/4x LP-Serial interface (Rev. 1.1), enabling data rates of up to 20 Gbps. Customers using Leopard Logic's cores can start with the implementation of designs targeting RapidIO immediately, while the specification is still awaiting final ratification and changes are still possible. The platform is built around an embedded FPGA core that is used to implement the control and protocol logic which are still likely to change as the standard matures, while timing critical blocks such as 8B/10B SERDES, PLLs and well defined functions
like CRC checks, memories and register files are implemented in standard cells.
Credence Systems Corp. introduced Octet, its next-generation, high-performance SoC test platform that can be configured with digital capabilities of 400 Mbps, 800 Mbps, and 1.6 Gbps, together with a variety of analog instrumentation, the company said. Octet's standard 1024 pin architecture can be configured with options for multiple data rate digital test capability, high-speed serial test, and a full suite of analog instrumentation. Octet is also compatible with Credence's Quartet Series. Octet also features a fully integrated software suite that is optimized for design-to-production test. The suite includes test development software, as well as virtual test and debug tools from
Integrated Measurement Systems, Inc. (a Credence company). Further, Octet's Program Developer provides a graphic user interface to enable the software modules in the suite to share a single interface for all test program development tasks, saving programming time by eliminating unnecessary steps.
IMEC, the independent European R&D center for microelectronics, has established a Reliability Center to build on the framework of its research activities in physics of failure mechanisms, reliability test structures and test methodologies, and built-in reliability. The new Reliability Center is equipped with a wide range of reliability test systems and systems for failure and material analysis. With this new center, IMEC said it would address the economic demand for increased reliability levels of next-generation semiconductor devices and microsystems. The reliability center is looking for collaboration with industry and research centers on innovative, in-depth research of specific
topics in the area of reliability and failure physics. Potential partners are equipment manufacturers, semiconductor and microsystems manufacturers, packaging houses and fabless companies, IMEC said. Collaborations will be performed on a bilateral base in which cost and IP will be shared.

Altium Limited has acquired the EDA business of Hoschar AG, the leading German distributor of EDA tools, in order to consolidate and increase Altium's market share in Europe, mostly in Germany. Altium said Germany is the largest EDA market in Europe and the second largest worldwide behind the USA. Over the past 14 years, Hoschar has introduced and implemented one of the most sophisticated and successful distribution channels in the EDA industry and has dominant market reach to electronic design professionals in Germany and Austria. It has also developed a highly automated and integrated direct marketing and telesales platform that has played a significant role in establishing
the company as the leading EDA distributor in Germany. With the acquisition of Hoschar, Altium said it will strengthen its position in Europe by utilizing Hoschar's key strengths and expertise in customer relationship management, in the integration of direct marketing and sales of EDA tools, and in launching EDA products into German and other European markets. The companies believe the acquisition will benefit Hoschar customers by providing long-term stability in the product lineup, and will give them direct access to Altium's comprehensive range of desktop EDA software and support services.
Hudson Soft said it has licensed MoSys Inc.'s 1T-SRAM embedded memory technology to develop its next generation advanced products incorporating high performance, high density embedded memory blocks.
MoSys also announced that SwitchCore AB has licensed its 1T-SRAM embedded memory technology for use in SwitchCore's products, which are key components for high data throughput applications, such as highly integrated switches and routers found in local, metropolitan and wide area networks.

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-- Ann Steffora, EDACafe.com Contributing Editor.