[ Back ]   [ More News ]   [ Home ]
July 22, 2002
EDA Week in Review
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Ann Steffora - Contributing Editor

by Ann Steffora - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

The U.S. Federal Trade Commission said it would not oppose Synopsys, Inc.'s acquisition of Avant Corp., even though some of the commissioners expressed fears that the deal could end up being anticompetitive. The FTC said the five commissioners voted unanimously to close the agency's antitrust investigation of the merger even though three of the commissioners indicated that action might have to taken later if there is evidence that Synopsys-Avant is stifling competition.
"I remain concerned about Synopsys' future conduct and possible market effects,” commissioner Mozelle Thompson said in a statement accompanying the decision. "Accordingly, if sufficient evidence comes to light, I expect that the Commission would promptly initiate appropriate action."
Two other commissioners also said the FTC should keep a close eye on Synopsys. Commissioner Sheila Anthony urged the company's customers and competitors "to keep the commission fully appraised of post-acquisition market developments, in case a future enforcement action becomes necessary."
FTC officials took the unusual step of continuing their investigation of the Synopsys merger even after it allowed the companies to complete the transaction last month.
The FTC is concerned about the merger because with regard to whether Synopsys would be able to use its dominance in front-end tools to hamper competitors in the market for Avant's back-end tools. The companies argued that the merger would allow for tighter integration of Synopsys-Avant tools, which would allow for more efficient chip design.
Despite their concerns, the FTC concluded that there was not enough evidence to predict the merger would have anticompetitive effects.
Synopsys and inSilicon Corp. signed a definitive agreement for Synopsys to acquire all outstanding shares of inSilicon for approximately $64 million. The transaction will be effected by means of a cash tender offer for all of the outstanding shares of inSilicon. The offer is subject to certain conditions, including the tender of a majority of the outstanding shares of inSilicon, receipt of regulatory approvals, and other customary conditions.
According to Synopsys chairman and CEO Aart de Geus, the acquisition of inSilicon provides customers with access to a strong portfolio of open format, digital and mixed signal connectivity IP. Synopsys DesignWare IP Library users had been asking for access to more complex IP as standards have evolved. inSilicon was first to market with high-quality IP for leading standards such as USB, PCI, Ethernet, and 1394 and the addition of this company will enable Synopsys to offer customers the widest possible range of IP solutions at the highest level of quality, the company said further.
The acquisition will be effected by means of a cash tender offer for all of the outstanding shares of inSilicon at a cash purchase price of $4.05 per share, followed by a back-end merger in order to purchase any untendered shares. Synopsys will also assume certain inSilicon stock options in the transaction. Phoenix Technologies, which owns approximately 69 percent of the outstanding shares of inSilicon, has agreed to tender those shares to Synopsys.
More tragic developments in the HPL Technologies, Inc. scandal include the company reporting that it has uncovered a massive accounting fraud involving "fictitious transactions" and "falsified documents" that were apparently orchestrated by its founder and former CEO David Lepejian.
The company, which went public a year ago, also said much of the money reported as cash on its balance sheet "is not now, and may never have been, in the company's possession."
Elias Antoun, a company director and acting CEO put most of the blame on Lepejian during a brief teleconference, and said the company is still investigating whether other officials were involved.
Interestingly, HPL said Lepejian's whereabouts are unknown and that it has not been able contact him since he left company offices. Lepejian, 41, had been president and CEO since he helped start the company in 1989.
NASDAQ suspended trading in HPL shares, and now the company faces possible delisting from the stock exchange.
HPL said that at least $11 million of the $13.7 million HPL reported as revenue in the fiscal fourth quarter ended March 31 was based upon "fictitious transactions supported by falsified documents," Antoun said.
The deals in question were booked as sales to HPL's Japanese distributor, Canon Sales Co., a unit of Canon, Inc. even though Canon reportedly never agreed to enter into these transactions.
The Canon sales accounted for $29 million (78 percent) of the revenue HPL reported in the fiscal year ended March 31, 2002. In the prior year, Canon Sales was $5.8 million (43 percent) of HPL's reported revenue.
Statements from the company indicate this may not be the full extent of the problem and that it expected to restate results for the fiscal year ended March 31 and possibly for the previous year, when it was still a privately held company.
To make matters more complicated, the following law firms have filed class action lawsuits against the company and Lepejian: Weinstein Kitchenoff Scarlato & Goldman Ltd.; Weiss & Yourman; Abbey Gardy, LLP; Milberg Weiss Bershad Hynes & Lerach LLP; Schiffrin & Barroway, LLP; Cauley Geller Bowman & Coates, LLP; and Glancy & Binkow LLP.
Cadence Design Systems, Inc. and PolarFab, a U.S.-based pure-play semiconductor foundry, announced final acceptance of the Cadence-developed process design kits for PolarFab's ABC/RFBC analog BiCMOS processes. PolarFab's ABC and RFBC process families support chips running in excess of 1.5 GHz and can safely handle 10 V supplies.
Synopsys, Inc. announced the availability of ViewConnect online customer support, which enables customers to collaborate with Synopsys to solve tool and methodology issues in real time via a secure Internet connection, the company said.
ViewConnect provides a secure, direct link between the user's desktop and Synopsys support personnel to make it possible to resolve problems in context, using the customer's actual libraries and design environment.
Mentor Graphics Corp. and Xilinx, Inc. announced an agreement to develop a customized extension to the Seamless co-verification environment, optimized to the requirements of designers embedding the PowerPC 405 Core into Virtex-II Pro devices. The collaboration goal is a co-verification solution optimized for Xilinx FPGAs that will significantly ease the adoption of co-verification technology into the Xilinx design flows.
The Seamless Virtex-II Pro solution builds upon the Seamless co-verification environment and the PowerPC 405 Seamless processor support package, the companies explained. Encapsulating knowledge of the Virtex-II Pro devices within this co-verification solution is aimed at reducing integration time, enabling designers to be more productive in a shorter amount of time.
The Platform FPGA will be part of a complex system that will also require verification, and will often contain other processors and DSPs.
Accelerated Technology, the embedded systems division of Mentor Graphics Corp. said that its Nucleus Real-Time Operating System (RTOS) was selected by PENTAR Avionics to develop the CMS-1000 communications management system for use in airborne transportation. The CMS-1000 is a device employed to manage communications between an aircraft operator and ground control.
Development of the CMS family included Nucleus PLUS, a scalable real-time kernel; Nucleus NET, a full-featured TCP/IP protocol stack; Nucleus FILE, a file management system; Nucleus PQUICC Ethernet driver; and the Nucleus Extended Protocol Package.
Magma Design Automation, Inc. expanded its sales and support operations in Taiwan with a new facility and Alex Chu joining as regional sales director for Taiwan operations. Chu, who previously managed sales in Taiwan for Avant! Corp. and Synopsys has an extensive track record in the semiconductor and EDA industries and will be responsible for accelerating Magma's growth in Taiwan, Magma said.
Magma said it new facility in Hsinchu is its first direct-sales office in the Asia-Pacific region and will enable Magma to offer strong technical support to its customers there and provide closer alignment with the area's leading foundries. It also offers the potential for a research and development center in the near future, closer alignment with leading foundries in Taiwan and expansion into mainland China, the company believes.
Chu's most recent experience was as head of Taiwan sales for Avant!. He also served briefly as a sales manager for Synopsys Taiwan, following Synopsys' June acquisition of Avant!, before leaving to join Magma. Chu's experience also includes a tour of duty with Cadence Design Systems where he spent eight years in application engineering and sales positions. He began his professional career with Industrial Technology Research Institute where he was one of the early hardware designers in Taiwan to use Verilog-XL and top-down design flow for hardware design. Chu holds a B.S. degree in computer engineering from Feng-Chia University in Taiwan.
Magma also announced new design-for-test (DFT) capabilities for the Blast Chip RTL-to-GDSII design system are currently in beta testing and will be available in the fourth quarter of 2002.
The company believes that the addition of DFT capabilities to Blast Chip makes it the only EDA provider able to offer designers a single RTL-to-GDSII chip implementation system that integrates DFT analysis and repair capabilities with logic synthesis, and that is based on a unified data model architecture.
The DFT option to Blast Chip enables the system to insert test structures during design implementation, Magma explained, which ensures that the entire design, including the test structures, is optimized throughout the implementation flow for timing, area and power.
Thirdly, Magma reported that Faraday Technology Corp. would license its RTL-to-GDSII flow, including signal integrity capability, for deep-submicron ASIC design. This agreement follows Faraday's in-depth evaluation of Magma technology over the last few months, including several pilot projects aimed at defining a more productive design flow for Faraday's 0.18-micron and more advanced technologies.
Faraday and Magma said they would work together to integrate Magma tools with Faraday's in-house EDA tools, and construct design kits that incorporate Faraday's advanced ASIC cell libraries targeting wafer foundry, memory compilers, processor cores and other analog/mixed-signal IP blocks.
Developed in conjunction with Oki Semiconductorand the Pittsburgh Digital Greenhouse, Neolinear announced the availability of NeoIP, a soft analog IP library that can be used for analog and mixed-signal (A/MS) designs. NeoIP is used with the company's next generation A/MS design flow and is included with NeoCircuit, for automatic analog circuit sizing, and NeoCell for automatic analog cell place and route.
NeoIP contains sized schematics and verified layouts of analog circuits including popular topologies for voltage controlled oscillators, phase frequency detectors, opamps, etc. These example circuits have been sized to commercial specifications utilizing a generic process design kit. NeoIP circuits can be used to build complex analog blocks such as phase-locked loops or data converters. All designs have been automatically sized with NeoCircuit and placed and routed with NeoCell.
LogicVision, Inc. expanded its global distribution with the selection of D'Gipro Design Automation & Marketing Pvt. Ltd., as the exclusive distributor for LogicVision products in India. Under the agreement D'Gipro will sell LogicVision's Embedded Test 4.0 product line and provide marketing and technical service throughout India.
Monterey Design Systems announced that Dr. Olivier Coudert, senior technologist for Monterey, was recently presented with a "SIGDA Technical Leadership Award" for his efforts on behalf of the SIGDA (Special Interest Group on Design Automation) Ph.D. Forum. Coudert co-founded the forum 5 years ago.
The Ph.D. Forum is now the largest Ph.D. and industry exchange forum in the EDA industry. It is held annually at the Design Automation Conference. This year's forum at the 39th DAC in New Orleans drew more than 500 attendees. The Ph.D. Forum is a session hosted by SIGDA for Ph.D. students to present and discuss their thesis work with people in the design automation community. It is an opportunity for the Ph.D. students to get feedback on their work and for the industry to preview academic work in progress.
Coudert has been with Monterey for 4 years and is responsible for Monterey technology used throughout the entire product line - timing analysis, logic optimization, placement, and clock tree synthesis.
ReShape, Inc. completed its Series B financing. The round was $12 million in cash, which brings the company's total venture financing to $18.5 million since it's founding in 1997. Canaan Partners (Rowayton, Connecticut and Menlo Park, Calif.) led the investment, with Series "A" investor New Enterprise Associates (Menlo Park) participating. Jim Furnivall, general partner of Canaan Partners, joins Mark Perry, general partner at NEA, and Moshe Gavrielov, CEO of Verisity, as outside directors. Reshape has used its technology to complete two high-performance multimedia chips, a 3800 pin switch fabric, and a mixed-signal chip. Current projects include a wireless communication
chip, an image processor and two wireline networking chips. Financing proceeds will be used to expand the company's physical design center and advance the technology.
Avnet Design Services (ADS), the technical arm of Avnet Electronics Marketing, and Xilinx Inc. announced a new development kit for the RapidIO interconnect, which includes a PowerQUICC MPC857T processor from Motorola and a Xilinx Virtex-II Platform FPGA, aimed at giving designers the flexibility to quickly and easily develop systems based on RapidIO interconnect technology -- accelerating the development cycle by as much as several months.
RapidIO interconnect technology is a switched, high-speed, low-latency packet-based, point-to-point mezzanine bus for processors, memory and IO. RapidIO technology reduces pin counts, while staying full duplex, and uses LVDS signaling.
The RapidIO Development Kit contains two Xilinx Virtex-II development boards, two Motorola 857T processor boards, the Xilinx Rapid I/O Physical Layer Interface, complete design documentation, demonstration programs, and a board support package to simplify application development.
Tensilica, Inc. hired industry veteran Paula Jones as director of corporate communications. Applying more than 20 years of experience in marketing communications, public and investor relations for numerous semiconductor and EDA companies, Jones will spearhead Tensilica's worldwide communications programs. Jones replaces Kim Alfaro, who retires after working with the company since shortly after it was founded.
Prior to founding her own firm, Jones held director-level positions with a variety of companies including MMC Networks, Synopsys and Cirrus Logic.

You can find the full EDACafe event calendar here.

To read more news, click here.

-- Ann Steffora, EDACafe.com Contributing Editor.