November 18, 2002
Cadence and Synopsys Settle Longstanding Avant! Trade Secret Theft Case
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
| by Ann Steffora - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!
Just when it appeared they would actually take it to a courtroom trial, Cadence Design Systems, Inc. and Synopsys, Inc. settled the lengthy litigation known formally as “Cadence Design Systems, Inc. et al. v. Avant! Corporation et al.,” in the United States District Court for the Northern District of California.
Per the settlement, Cadence will be paid $265 million. In addition, Cadence, Avant! and Synopsys, as the acquirer of Avant! have entered into reciprocal licenses covering the intellectual property at issue in the litigation.
Ray Bingham, president and CEO of Cadence said the settlement “underscores the integrity of the laws that protect and thereby enable innovation. With the litigation behind us, our resources -- and those of Synopsys -- can be more focused on providing solutions for the technology challenges faced by our customers. I believe that the electronic design industry now can move forward in a spirit of cooperation and healthy competition.”
Dr. Aart de Geus, chairman and CEO of Synopsys add that while they do not condone the actions taken against Cadence in the past by Avant!, they also acknowledge the damage that it has caused to Cadence. “Today's agreement puts this matter to rest for good. We are pleased that we were able to work constructively with Cadence in order to resolve this matter. We are hopeful that the settlement will open a new chapter to a more mature and healthier electronic design industry going forward.”
Cadence will be paid $265 million in two installments: $20 million to be paid on or before November 22, 2002, and $245 million to be paid on or before December 16, 2002. The amount will be paid by Illinois National Insurance Company, a subsidiary of the American International Group (AIG), insurer for Synopsys, under an insurance policy purchased by Synopsys upon the completion of its acquisition of Avant!
Aptix Corporation rolled out Aptix Prototype Studio, which the company reported extends the benefits of Aptix prototyping technology to developers of custom multi-FPGA PCBs and has support for Aptix prototyping products: System Explorer and Software Integration Station (SIS). It provides a complete RTL to pre-silicon prototype (PSP) flow, regardless of whether the target is a hardwired or reconfigurable PSP.
Aptix Prototype Studio includes Aptix Design Pilot, supports partitioning a monolithic SoC design across multiple FPGA devices, works within the pin constraints of the FPGAs, maps SoC constructs like gated clocks into structures more appropriate for FPGAs, and debugs with the PSP when problems are uncovered in the design, the company said. Aptix Prototype Studio supports the latest Xilinx FPGA devices.
Aptix Prototype Studio is available in three forms.
Aptix Prototype Studio/PCB is available to designers targeting only hardwired PCBs.
Aptix Prototype Studio/Pro supports Aptix traditional reconfigurable prototyping products, System Explorer and Software Integration Station.
Aptix Prototype Studio/Enterprise supports all hardware targets.
Additionally, the link from the Aptix prototype database to a hardwired PCB utilizes FPGA Connector from Translogic, which automatic creates homogeneous and heterogeneous symbols to interface to industry standard schematic editors, in order to reduce the setup requirements for symbol creation into minutes. The link converts HDL descriptions into pin constraints for FPGAs and includes version management to ensure database consistency and accuracy. This use model promotes parallel engineering efficiency for schematic entry, FPGA place-and-route and board layout, the company said.
XYALIS introduced GTsmooth, a hybrid metal-fill tool to address CMP issues. GTsmooth uses a model-based approach to identify where dummies must be inserted and follows a rules-based approach to determine how to insert dummies, to minimize thickness variation over chips and wafers, limit CMP effects and increase yield.
To determine areas where dummy tiles need to be inserted, GTsmooth evaluates the thickness variation over the chip with a proprietary post-CMP thickness estimator, based on XYALIS' years of experience in the CMP domain. The GTsmooth approach is highly flexible and supports any process, since users may plug-in their own post-CMP thickness estimation function, based on the foundry expertise.
To limit the number of added dummies, reduce the parasitic capacitance variation and minimize performance degradation, XYALIS has implemented a patented algorithm for metal-fill that makes sure that a minimum number of dummies are only added where needed. GTsmooth inserts up to 95 percent less tiles than rules-based tools for maximum yield improvement, the company said.
GTsmooth inserts a small number of tiles, regularly spaced, so that the computation time is fast without database explosion, enabling designers to insert dummy tiles early in the design process and take their parasitic effects into account during timing verification.
A last dummy tile insertion step is usually required at wafer level just prior to manufacturing after the process engineer adds test and alignment features to sawing lines. This last modification to the layout breaks the regularity and dramatically increases the size of the wafer-level database. XYALIS' optimizations in terms of computation time, memory and disk usage allow GTsmooth to handle such wafer-level dummy tile insertions.
0-In Design Automation announced CheckerWare monitors for the AGP 8x, HyperTransport, InfiniBand and RapidIO standards. Leading IC design teams and ABV users can increase verification productivity by utilizing these pre-verified Verilog register transfer level (RTL) monitors to validate compliance with the latest protocol and interface standards, the company asserted.
CheckerWare monitors are developed with leading customers as part of 0-In's continuing commitment to promote industry standards through the support of open standards. The capabilities of 0-In monitors include formal tool support, testbench and simulator independence, and interoperability with all tools in existing verification environments. Using 0-In's CheckerWare monitors, designers eliminate the time spent on developing and debugging protocol monitors and are free to devote more time to design and verification.
CheckerWare monitors certify that the designs conform to interface standards and enable products to be interoperable with all products that support these standards. During simulation, CheckerWare monitors warn users of any protocol violations and generate structural coverage statistics to measure testbench efficacy. The same monitors serve as targets and constraints to guide formal verification tools, including the 0-In Search dynamic formal verification tool.
Ewald Detjens assumed the role of CEO at Circuit Semantics Inc. Detjens is founder of synthesis provider Exemplar Logic Inc., now part of Mentor Graphics Corporation. In a related move, Detjens has restructured Circuit Semantics to grow the business, increase revenue, expand the customer base and extend its product offerings. Jose Torres has become Circuit Semantics' vice president of marketing.
Detjens, a resident of San Francisco, founded Exemplar Logic in 1987. Mentor Graphics acquired Exemplar Logic in 1995, where he remained through 1997. Detjens became a private seed investor in various software companies until January 2002, when he became interim CEO of Bridges2Silicon. Previously, Detjens worked for Philips Research Labs and STC Computer Research. A graduate of the University of California at Berkeley, Detjens holds a Bachelor of Science Degree in Computer Science and a Master of Science Degree in Electrical Engineering.
ReShape, Inc. announced that Professor Andrew B. Kahng, Ph.D., of the University of California at San Diego, has joined the company's technical advisory board. Kahng is Professor of Computer Science & Engineering and Electrical & Computer Engineering at UCSD. He actively researches VLSI physical design, the design-manufacturing interface, and design process optimization; he also leads initiatives in CAD-IP reuse, technology extrapolation, and metrics within the Gigascale Silicon Research Center (GSRC).
Kahng chaired the Design Technology Working Group for the 2001 and 2002 editions of the International Technology Roadmap for Semiconductors (ITRS), and defined the physical design roadmap as a member of that working group for the 1997, 1998 and 1999 renewals of the ITRS. Full biographical details for Kahng can be found at
ReShape's TAB membership also includes Forest Baskett, Ph.D., Venture Partner and former Silicon Graphics, Inc. CTO; Mark Horowitz, Ph.D., Professor Electrical Engineering, Stanford University and Rambus, Inc. founder; Kurt Keutzer, Ph.D., Professor Electrical Engineering at U.C. Berkeley, former CTO at Synopsys, Inc.; and Richard Newton, Ph.D. Professor and Dean U. C. Berkeley, School of Engineering.
Magma Design Automation Inc. named Dr. Ron Rohrer to the position of chief engineer, reporting to Magma President and COO Roy E. Jewell. Rohrer, a long-time EDA visionary, joined Magma in January as an adviser on corporate strategy and will now work full time for the company, with principal responsibility in advanced product research.
Rohrer was also honored this month as the 2002 winner of the Phil Kaufman Award, given annually by the Electronic Design Automation Consortium to an individual who has contributed to creating or driving technology advances that have had measurable impact on the productivity of design engineers.
A world-renowned expert in the semiconductor and EDA industries, Rohrer serves as chairman of Neolinear in Pittsburgh, Pa., and as a board member of Lambda Technologies in Raleigh/Durham, N.C. He started his industrial career at Fairchild Semiconductor in the 1960s, and has since served as a technical consultant and adviser to leading EDA and electronics companies, including IBM, AT&T Bell Laboratories, Synopsys, Avant!, Mentor Graphics and Cadence Design Systems. Rohrer founded Performance Signal Integrity, which Integrated Silicon Systems acquired before merging with Arcsys to form Avant! Corporation. He has served on the
boards of directors for numerous successful technology startup companies, including ISS, Genesis Microchip, interHDL, Performance Signal Integrity, Technology Modeling Associates, Comstock Systems and Xynetix Design Systems.
Prior to his present positions he was an educator and an entrepreneur, and has held research, marketing and management positions in large and small semiconductor and EDA companies over a span of more than 35 years. In the early 1960s Rohrer began using optimization techniques for the design of ICs, and in 1989 he was inducted into the National Academy of Engineering for his “contributions to circuit simulation that enabled deep-submicron IC design.” Among his many awards are the 1996 NEC Computer and Communication Prize, a worldwide honor for pioneering contributions in electronics, the 1993 IEEE Education Medal, the SRC Inventor Recognition Award in 1990
and the ASEE Terman Award in 1978. He is a fellow of the IEEE, and author of five textbooks and more than 100 papers.
A new milestone has reportedly been achieved in the technology partnership between semiconductor manufacturer X-FAB of Erfurt, Germany and Mentor Graphics Corporation. The Mentor Graphics Calibre tool suite will now be included in X-FAB's mixed-signal solutions offerings and X-FAB will continually integrate the new tools for mainstream processes in their design kits and provide requisite support.
X-FAB will offer its customers complete Mentor EDA support for the newly developed X-FAB master kits, which support the complete Mentor verification product line with the Calibre DRC and Calibre LVS tools for physical verification and the xCalibre tool for parasitic extraction, as well as the newest simulation tools based on the Mentor Graphics IC Flow and Design Architect-IC, including the ADVance MS, Eldo and ModelSim tools.
At first, the expanded mixed-signal kit for the 0.8 um high-voltage technology CX08H will be available, with plans for all X-FAB processes to be expanded to include the complete Mentor Graphics design environment.
Hitachi, Ltd. has licensed MoSys' 1T-SRAM embedded memory technology. Under the terms of the agreement, MoSys' 1T-SRAM memory technology will be embedded in Hitachi's wide-range of semiconductor products. Norio Miyake, general manager, System Solution Planning Dept., Semiconductor & Integrated Circuits at Hitachi, Ltd. said, “MoSys' 1T-SRAM memory solution delivers Hitachi unique quality capabilities not found in other memory technologies. This will enable us to develop higher-quality chips, thus increasing our market leadership and continuing to provide top-of-the-line electronics.”
Neolinear, Inc. announced that Toshiba is deploying NeoCircuit for widespread production use to automate the sizing of their custom circuits. This agreement follows Toshiba's in-depth evaluation of Neolinear's technology over the last several quarters, including several pilot projects aimed at defining a more productive mixed-signal design flow for Toshiba's 0.14-micron and other advanced technologies.
“The combination of NeoCircuit and NeoCell provides us the ability to create and re-use mixed-signal IP. We look forward to working with Neolinear to further streamline our design flow based on these new technologies,” said Takashi Yoshimori, General Manager of Toshiba's System LSI Design Division.
Axis Systems, Inc. announced that AVC Company, Matsushita Electric Industrial Co., Ltd. used the Xtreme verification system from Axis to increase the quality and reduce verification time of an image processing chip for Matsushita's DIGICAM NV-MX5000 digital video camera.
The new chip is a system large-scale integration (LSI) chip that contains more than 1.3 million logic gates and more than 20 Mb of embedded DRAM. The chip, which uses the Advanced Pixel Interpolation System (AXIS) technology that Matsushita developed, is the first to enable a digital video camera to record three-million pixel still images with extremely high resolution and outstanding image quality. In addition to the AXIS technology, the camera system also uses three charge-coupled devices (CCDs), giving it the quality of a professional broadcast video camera.
Xtreme, which integrates software simulation, accelerated simulation, and emulation in one system, enabled Matsushita designers to run long tests on the chip, vastly improving verification results over their previous software simulation solution. Because the chip was thoroughly verified, Matsushita achieved first silicon success.
Koichi Toyomura, Staff Engineer in the AVC Network Business Group, AVC Company, Matsushita Electric Industrial Co., Ltd. said Xtreme was very easy to adopt, and it was incorporated into the company's current methodology with very little effort, and it came up in acceleration mode in half a day.
Circuit Semantics Inc. said that Sun Microsystems, Inc.'s Processor and Network Products (PNP) Group has signed a license agreement for Sun to use CSI's EDA software products.
Corporate News & Partnerships
Artisan Components, Inc. announced that its libraries are available with signal integrity (SI) and noise analyses support using noise modeling capabilities in Synopsys' Liberty open library standard. The support of noise modeling for Artisan's libraries is aimed at delivering more accurate modeling timing, crosstalk and noise analysis, in order to enable a more reliable 130-nanometer (nm) and below design flow.
Artisan and Synopsys said they have collaborated to define the new noise modeling capabilities in the Liberty open library standard and to implement and test these capabilities at tool and library levels. Beta testing for tools and libraries with mutual customers is expected to start before the end of 2002, initially with 130-nm libraries.
Additionally, Artisan said its libraries would support Synopsys' scalable polynomial delay model (SPDM) to increase the accuracy and capacity of timing analysis in Synopsys' EDA tools. This addresses the need for increasingly accurate modeling of voltage and temperature effects without sacrificing tool efficiency and allows for advanced capabilities like IR drop analysis and multi-voltage design. SPDM libraries will be available from Artisan upon customer request.
Synchronicity Inc. and INNOTECH Corporation signed a software distribution agreement. INNOTECH will sell the Synchronicity Developer and Publisher Suite solutions for design management, collaboration, and reuse. INNOTECH is also the exclusive distributor of the Cadence design automation tools in Japan. In Synchronicity's Physical Developer Suite, the design management tool, DesignSync, is directly integrated into the user interface of key Cadence tools, such as Composer and Virtuoso, and has special awareness of the Cadence software's complex file behaviors, the companies said. The Developer Suite was also recently completely localized for the Japanese market.
ARM, LSI Logic, Infineon Technologies and PMC-Sierra and have joined Verisity Ltd.'s LicenseE program. As members in the LicenseE program, each company will receive open access to the e language and will participate in the e Steering Committee. The Steering Committee's purpose is to drive the e language to standardization to better serve the verification market. All companies on the Steering Committee have equal say, including Verisity. Currently participating in the program are Verisity customers including: ARM, Cisco Systems, Infineon Technologies, LSI Logic, PMC-Sierra, and STMicroelectronics.
AccelChip, Inc. signed an agreement for Marubun Corporation to serve as its exclusive distributor for the AccelFPGA products, methodologies and services in the Japanese market. AccelFPGA is the first DSP design tool that directly synthesizes the MATLAB design language, the language used by the overwhelming majority of DSP designers, the company said.
@HDL, Incorporated announced that Fujitsu Labs of America (FLA) has become the newest member of the @HDL Technology Alliance Program. FLA will work with @HDL in the area of functional verification. The FLA SoC engineering and design automation tool development groups will work closely with the @HDL technical staff to further enhance functional verification methodologies and capabilities. The initial collaborative projects are focused in the areas of formal model checking and assertion-based verification.
Synplicity, Inc. acquired the FPGA debug product, core technology and other intellectual property from Bridges2Silicon, Inc. Synplicity said it plans to sell the standalone FPGA debug product and intends to apply the underlying technology for the development of next-generation debug products. Synplicity completed the asset acquisition for cash consideration of $2,500,000.
As part of the product and technology acquisition, Synplicity also hired three members of the EDA development team that created the debugger product and technology. These new employees will join Synplicity's FPGA synthesis and RTL prototyping product teams to develop next-generation products based on the debugging technology. Synplicity said it plans to sell the Bridges2Silicon Debugger software as part of a new Identify family of debugging solutions.
A free NanoCool online seminar on Wednesday, November 20, 2002 at 11 A.M. PST, will offer an examination of low-power IC design issues, while detailing the tools and techniques necessary for success in the sub-100 nanometer realm, according to Sequence Design, Inc.
Registration for the seminar, sponsored by Sequence Design, a founding member of the NanoCool Initiative for low-power design, is now open online at:
According to Dr. Susheel Chandra, Sequence senior vice president of R&D and product marketing, concerns over power consumption are no longer limited to designers of ICs for portable applications, but for other types of design as well.
Power reduction techniques are applied at every stage of low-power design, with analysis serving as a gauge for the amount of power reduced. In a power-management flow, early analysis guides the power reduction efforts. At the final stages of the design process, power analysis is again used to ensure that the power specification is met, or that power wastage has not been introduced.
Additional information about the low-power seminar and other Sequence events may be obtained via e-mail at
An upcoming panel of industry CEOs will discuss the benefits, concerns and intricacies of COT design. Companies are looking for ways to design themselves out of the economic crisis, knowing they need to be sharper than the competition. Monterey has put together this panel of electronics industry leaders to address how to reduce risk, maintain security, improve performance and turn around time, and innovate by implementing COT design.
When: Thursday, November 21, 2002 at 4:30 PM
Where: The Westin Hotel in Santa Clara
Registration begins at 4:00 PM. A Q&A discussion with wine and hors d'oeuvres will immediately follow the panel.
Jacques Benkoski, president and CEO of Monterey Design Systems will give a keynote address.
Mark Templeton, president and CEO, Artisan Components
Jack Harding, Chairman, president and CEO, eSilicon
John Bourgoin, Chairman and CEO, MIPS Technologies
Yoav Nissan-Cohen, Co-CEO, Tower Semiconductor
Levy Gerzberg, president and CEO, Zoran
Erach Desai, an electronics analyst with American Technology Research, will moderate the panel.
The first edaForum will take place in Hannover, Germany on December 5th and 6th, 2002. Organized by the edacentrum as part of its mission to overcome the design gap by collaborative actions among system and semiconductor companies, EDA vendors and research institutes, the edaForum02 will bring together decision makers from industry and top-rated speakers from all over the world. Information about the program of this event, the speakers and the location can be found at
Agilent Technologies will hold a free, interactive Web seminar for software/hardware integration and software verification engineers and protocol and application software developers to discuss new tools for cell phone software applications, such as Web browsers, games, cameras and operating systems. The seminar, titled, “Network Emulation Speeds Design of Wireless Devices/Applications,” will give an overview of wireless handset design trends, including verifying each design's connection to the Internet, emulating the real-world RF environment and monitoring messages over the air.
The seminar will take place December 6, 2002, from 6 A.M. to 7 A.M. P.T. or 9 A.M. to 10 A.M. P.T.
For more information, to register for a live seminar or to view an archived seminar, visit
Mentor Graphics is accepting entries for its 2003 PCB Technology Leadership Awards University Scholarship. Co-sponsored by HP, the scholarship is designed to promote innovation and excellence in education for printed circuit board (PCB) designers at colleges and universities. The winning entry in the Leadership Awards program's University & Training Institutes category receives an academic scholarship totaling $2,000.
The University Scholarship is open to any full-time undergraduate or graduate student (or team of students) at a college or university participating in the Mentor Graphics Worldwide Higher Education Program. A panel of industry-leading expert judges will evaluate each entry for innovation, complexity, physical design and aesthetics. University & Training Category entries are due by December 10, 2002, and award winners will be notified on or before January 31, 2003.
For more information on the Mentor Graphics Higher Education Program and the 2003 PCB Technology Leadership Awards Scholarship visit:
To read more news,
You can find the full EDACafe event calendar here
To read more news, click here
-- Ann Steffora, EDACafe.com Contributing Editor.