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February 24, 2003
Virtual Snow Day
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Geek Fest in the Age of Aquarius

What's fair is fair. If the entire Eastern Seaboard gets to shut down on account of weather, why should those on the West Coast have to venture out to earn a living? Besides, this is the Age of Connectivity. So stay home, log on, tune in, and find out what's up in the world around you.

Let's start with Craig Barrett. He's CEO of Intel Corp. and he hosted the Intel Developer Forum Conference at the San Jose Convention Center. It doesn't matter that you weren't there because, wherever you are in the world, you can see him delivering his keynote address. It's archived. It's on-line. It's free for the viewing. And it's pretty cool.

But in the Age of Irony - the corollary to the Age of Connectivity - you can't just watch Barrett speak. You gotta critique what he's saying and how he's saying it.

Intel CTO Patrick Gelsinger starts out by welcoming the 4000 attendees to the “The Greatest Geek Fest on Earth” and then introduces Barrett as the “Convergence Cowboy.” (Now, that's really less about the technology that Intel's promoting and more about the CEO as Celebrity. Because on top of everything else, this is the Age of Celebrity - and CEOs, like it or not, are indeed Celebrities.) So Barrett gets underway and takes well over an hour to discuss convergence in computing and communication and along the way hints at a pretty interesting syllogism:

- Technology's good - great, even.

- The world is excited about technology.

- Excitement is tantamount to happiness.

- We're driving technology.

- Therefore, we're good because we're propelling the world to happiness.

Clearly, others might have a different take on Barrett's message, but this is a Snow Day - tantamount to a Free Day - and so my conclusions are just as valid as anybody else's. At least for today.

What else does Barrett say? Well for starters, he's got a pretty big bucket for what constitutes “technology.” Geophysics and railroads and Internet cafes are all “technology.” But, making shoes or butter or tilling the fields is also technology. In fact, technically speaking, any human endeavor is “technology” if it uses the human intellect to monitor, control, or alter the surroundings.

But when Barrett says “technology,” we all understand what he means. He means computing platforms that have “Intel Inside” and drive IT, manufacturing, distribution, or communication infrastructures. But that's okay. We'll let Barrett have a Snow Day, too. That's his conclusion and it's just as valid as anybody else's. At least for today. Besides, this is also the Age of Relativity - along with the Age of Connectivity, Irony, and Celebrity - and so everybody's opinion counts.

What else does Barrett say? Lots! He talks about the expanding IT markets and about the need to replace 160 million “old” PCs sporting Windows 95 and 98 because Microsoft will no longer support those operating systems after this year. (Nary a word here, however, regarding the ecological implications of adding yet another 160 million units to the growing pile of Planned Obsolescence that already litters the Globe.) He talks about the 1 billion people who will be using their 2 billion connected devices by 2005 or 2006, and about the legions of under-20-something-year-olds in the world who don't have the historical perspective to remember when the PC wasn't a part of life -
but happily have an “insatiable demand” for more digital music, video, and games.

He talks about the infamous “last mile” of connectivity between the Internet pipe and the private home and how, today, the costs for that last mile are more effectively addressed in Japan than in the U.S. He presents a fast-paced video clip full of CyberProfound house beat and excited voices from countries as diverse as Peru, Taiwan, Thailand, India, France, Vietnam, Brazil, Russia, Jordan, Chile, Australia and the U.S. all proclaiming their need and passion for “technology” and the improvements that pursuit of same will bring to their people, their culture, and their lives.

He chastises the American Press for being the “most down on technology” out of the Global Press, and for being out of sync with the rest of the world. He reviews revolutionary and evolutionary developments in technology over the last 50 years, discusses Moore's Law, and admires “smart engineers who will create the next revolutionary and evolutionary advances.” He extols the virtues of content creation and distribution for a plethora of digital media. And, of course, he speaks at length about the convergence between computing and communications being addressed by Intel and other such visionary organizations.

And there's more. Barrett brings a friend out on stage to demonstrate the magical merger of optical fiber technology and silicon computing in a CMOS sort of way, and a friend to demonstrate software-enabled noise filtering in microscopy for examining and manipulating nanometer-scaled devices, and a friend to demonstrate seamless integrations of technology across the “three screens” - the “couch potato's” big screen, the interactive PC screen, and the handheld small screen - empowering everyone from the “knowledge worker,” to the physician, to the amateur video editor, and entertainment entrepreneur. Then he brings out yet more friends to demonstrate the
benefits of compute-intensive visualization systems that address the needs of users from genome researchers to financial market analysts. And not surprisingly, through all of this, he manages to mention many of the latest silicon platforms coming out of the complex Intel R&D organization.

By the time Barrett wraps up, it's clear that this is way more than a keynote address. It's an attempt by Barrett and the entire Intel Marketing Team to exhaustively touch on every aspect of life that Intel is probing into - which is nothing short of computing “Anytime, Anywhere, with Any Device.” It doesn't get much more bold, inclusive, or time consuming than that. Even in the Age of Aquarius.

But why believe me? You, too, should take a Snow Day, click here, and find out for yourself. Your conclusions will be just as valid as mine or Barrett's. And that's a good thing.


Meanwhile, the technical gurus at Synopsys and Cadence and Magma are out there, as well, with their keynotes from last week's VirtualDacafe. They're also archived, on-line, and available on demand. If you're partial to EDA, their presentations are also well worth a visit and a Snow Day.

Cadence's Ted Vucurevich addresses “Nanometer Design Changes Everything”

Synopsys' Raul Camposano discusses “EDA and Manufacturing: The New Chapter in the Textbook”

Magma's Ron Roher reviews “The Evolution of Gate Modeling”

Their talks can all be accessed at

Meanwhile, back in the Age of Irony

One of the Intel Developer Forum speakers was apparently stuck on the East Coast due to the snow and a cancelled flight, and ended up being a no-show for a Tuesday afternoon panel. Given the circumstances, it's hard not to ask, “What's the problem here?” Why in the Age of Connectivity, Virtual Reality, and Streaming Media should a simple blizzard negate the oldest adage of them all - The Show Must Go On.

On the other side of the globe -- EDA in India

Thanks to STMicroelectronic's Gautam Awasthi - an Electronics Engineer working with ST (India) in its Strategic Marketing Division - for providing articulate answers to a variety of questions regarding EDA and the semiconductor industry in India.

Awashti starts: “India as a country is poised to become a major SoC and EDA player - both in terms of the development as well as in terms of the market.”

Although Bangalore may be the best known, there are many up-and-coming technology centers in India including Noida, Hyderabad, Madras, Gurgaon, and Mohali. The major EDA vendors and semiconductor companies have made substantial investments in all of these areas.

Meanwhile, the “brain-drain” which occurred in India in the early 1990's is now being experienced by the Americas and Europe. Experienced engineers are returning back from these continents to India. Although I have no specific data or figures with respect to the exact numbers of returning talent - with the increasing numbers of design houses cropping up in the sub-continent (even with the economic downturn), indications point towards a new breed of U.S./U.K.-returned entrepreneurs.

In fact, the global downturn has been a boon for the Indian sub-continent as both the EDA and semiconductor companies have closed down many shops in the U.S. and the U.K. and are making huge investments in setting up their centers in India (to compensate for lost R&D capabilities elsewhere). They view India as a low-cost, high-quality producer of manpower and talent. The two facts which support this claim are the cost of the Indian engineer (one-fifth of the U.S. engineer and one-third of the European engineer) and the quality of the Indian engineer by virtue of the country's excellent track record in technology education. (India has produced a large number of engineers, scientists, and

The Indian Institute of Technology (IIT), is a university system of six highly regarded Engineering Institutes, which together make significant contributions towards the EDA industry in terms of producing both developers and users. The major contributors in EDA among the six are IIT-Kharagpur, IIT-Mumbai, IIT-Delhi and IIT-Madras - where IIT-Madras has seen a fast paced growth in this area over the last few years.

Apart from the IITs, there are also other contributing institutions, including the Indian Institute of Sciences (IISc)-Bangalore, Birla Institute of Technological Sciences (BITS)-Pilani, and the Bengal Engineering College (BEC)-Calcutta, which have all been quite active lately in EDA. The above institutions, apart from producing skilled manpower, also engage in active programs of industrial research with the large EDA vendors and semiconductor companies. Over the years, they have developed in-house training processes that are relevant to these industries, as well. Annually, there are approximately 192,000 engineers graduating out of the various Indian engineering institutes, and of those
graduates, fully 40% are trained in disciplines related to IT and IC design - which translates to 80,000 graduates per year.

The technical universities in India use a range of vendor-supplied software, from PCB design tools to IC and FPGA design tools. The universities use all the best tools in the areas of design entry, simulation, and synthesis, etc. - but lack tools which address specialized applications (EMI/EMC, SI, noise, high-speed analysis, or other high-end analysis tools) or the very expensive tools (for instance, back-end tools in some cases). Design tools are acquired by the universities either through government grants or by way of donations from EDA vendors and semiconductor companies. Some of the EDA and semiconductor companies have also set up Design Excellence Centers in various universities
in India.

Design engineers in India are working in both VHDL and Verilog. For example, STMicroelectronics is a global semiconductor giant and a large consumer of EDA tools. The company has a large number of Customer Divisions working on specific customer projects. ST uses both VHDL and Verilog - the decision as to which language is left up to each Group/Division within ST. I see no particular preferences within these divisions for one language over the other. Instead, the preference may be based on the location of the Customer Unit - whether it is a U.S. customer/market or a European customer/market.

Industry News

Agere Systems announced the PayloadPlus APP540, a network processor that integrates four separate chips into one. The company says the new chip will reduce product development costs by 50% compared to equivalent market offerings. Korea-based Electronics and Telecommunications Research Institute is using theAPP540 processor as a basis for Korea Telecom's countrywide next generation network. The new processor integrates a programmable traffic manager, a multi-field classifier search engine, a network processor, and an Ethernet media access controller (MAC) onto a single device with processing speeds at 5 gigabits per second (Gbits/s). The company says classification, traffic
management, and network processing function like three different “traffic police officers” working in unison with separate yet inter-dependent functions. The classifier determines what should be done with the voice, data, or video information entering communications equipment and the network processor obeys processing and forwarding directions the classifier gives it. The APP540 chip is roughly one-fourth the size of a credit card.

Alcatel and Sun Microsystems, Inc. are announcing a new initiative aimed at service providers pursuing enterprise applications over wireless networks. The new project is part of an expanded relationship between the two companies who are working together on the establishment of a multi-device Java technology-based initiative for consumer and enterprise-focused service providers. Alcatel has been using its 3G Reality Centres to allow live tests on 2.5G and 3G network infrastructures while Sun has deployed its own iForce centres to allow end users and partners to test network applications. The companies say their joint effort is “device-agnostic” and is relevant to
devices from both the fixed and wireless worlds.

Also from Sun - The company announced a software test suite intended for Java technology-enabled mobile devices. The company says the worldwide deployment of 75+ million Java handsets over the past two years means there is a need for an off-the-shelf software test suite to replace in-house development and management of multiple tests for multiple handsets. With the Java Device Test Suite, individual handsets can be tested against 5000+ test cases in four different categories - functionality, stress, performance and sandbox security - and will allows users to plug in additional test suites for new APIs. The Java Device test suite is scheduled to be available in June 2003.

Altera Corp. announced the release of version 3.0 of the Nios embedded processor, which includes features based on the Stratix and low-cost Cyclone device families. The Nios version 3.0 includes: user-Configurable Caches, an enhanced SDRAM controller; the Avalon switch fabric; and a new JTAG-based real-time debugger; an integrated development environment; and a network protocol software library.

In related news - Altera announced the availability of the Nios Development Kit, Stratix Edition, which gives embedded designers a design platform for high-bandwidth system designs. The kit includes version 3.0 of the Nios embedded processor and the Stratix EP1S10 device. The kit also includes Quartus II development software, the SOPC Builder system development tool, and a suite of software development tools, as well as a Stratix development board with the Stratix EP1S10 device, 1Mb of SRAM, 16Mb of SDRAM, 8Mb of Flash, a 10/100 Ethernet port, two serial ports, a Mictor connector for software debug, two expansion headers, power supply, and download cable.

Altium Ltd. announced the TASKING TriCore VX-toolset, an embedded software development toolset intended to increase execution speed and decrease code size up to 10% over the current TASKING TriCore toolset. The new toolset has been developed for Infineon's 32-bit TriCore architecture and uses Altium's Viper compiler framework technology. The toolset is currently in beta testing and full public release is expected in April 2003.

Also from Altium - The company announced today the release of version 3.5 of the TASKING embedded software development toolset for Motorola's DSP56xxx architecture. Version 3.5 offers a redesigned user interface and support for the latest derivatives and evaluation boards, as well as re-arranged menu structures and improved dialogs, including flexible breakpoint configurations, and probe point support to allow data to be retrieved from, and injected into, an application at run-time using I/O simulation.

Applied Wave Research, Inc. (AWR) announced the relocation and expansion of the company's European headquarters at Lyon Court in Hitchin, UK. The new offices will maintain responsibility for managing sales representatives and providing technical support throughout Europe.

Artisan Components, Inc. announced the completion of its acquisition of NurLogic Design, Inc. Under the terms of the agreement, Artisan acquired NurLogic for approximately $5.0 million in cash and $12.7 million in stock. Artisan reserved approximately 822,000 common shares for issuance in connection with stock options assumed in the transaction.

Atmel Corp. announced the release of the AT91RM9200 microcontroller based on the ARM920T 200+ MIPS 32-bit RISC microprocessor from ARM Ltd. The microcontroller is upward-compatible with Atmel's family of ARM7-based microcontrollers and includes various configurations of on- and off-chip memories, along with a set of peripherals for control, communication, and data storage - including a USB host and device, Ethernet 10/100 Base T MAC, and interfaces for a variety of Flash cards. A power management controller permits a range of clock speeds and enables individual peripherals to be powered down when not in use. The AT91RM9200 is available in PQFP208 and BGA256 packages. Samples
are planned from April 2003.

Also from Atmel - The company announced an ultra-compact CMOS camera module, the Eye-On-Si for mobile phone and PDA applications. Eye-On-Si is the first product in a CMOS imaging product family that includes CIF, VGA, and megapixel sensors to be introduced throughout 2003. Eye-On-Si is a complete digital camera in less than 1/2 cubic cm and includes a single chip (sensor and image processor), a lens, a flexible cable, and all necessary peripheral components. The product is built on an Atmel package measuring 9.5x9.5x4.95mm. It is a 1/7-inch optical form on CMOS camera chip with 352x288 pixels. The module operates with a single 2.5V power supply within a frequency range from 3MHz to
80MHz. The on-chip image processing is based on Atmel's AVR technology. Most of the on-chip functions such as auto white balance, auto exposure control, color correction, flicker detection, and correction are programmable through a 2-wire serial interface. Atmel will also introduce in 2Q 2003 a camera module in VGA format that will have the same image quality, low size, image processing flexibility, and low power consumption as the Eye-On-Si product.

Cadence Design Systems, Inc. and Xilinx, Inc. announced the adoption of the Xilinx RocketIO Design Kit for SPECTRAQuest by 500+ designers and engineers. The kit is an electronic blueprint for simulating and implementing Virtex-II Pro Rocket IO transceivers in a system. The Xilinx RocketIO Design Kit is for the design, implementation, and verifications of GHz-speed serial links using multi-gigabit I/O technology, and for developing optimal constraints for PCB systems to drive PCB floorplanning, routing, and verification process. The design kit includes the following: system-level topologies for use of the device on the board/system; verified I/O buffer models; a large package
model; testbench data, correlation data; connector models for backplane applications; and device specific scripts/tools to evaluate simulation results.

Also from Cadence - The company announced that Texas Instruments (TI) has selected Cadence First Encounter physical prototype and placement system for use worldwide by its ASIC team. TI will integrate First Encounter into its flow for ASIC designs for the partitioning and time budgeting of high-performance ICs. TI also has integrated Cadence CeltIC into its ASIC design flow for sign-off crosstalk glitch analysis, and completed qualification work of Cadence's 64-bit 4.0 NC-SIM for chip simulation.

Concept Engineering announced the release of SpiceVision PRO, a turbo version of SpiceVision, an interactive visualization tool to debug and analyze SPICE circuits and models. Unlike SpiceVision, SpiceVision PRO is not limited to a certain number of components. SpiceVision PRO includes 64-bit support, a high-speed database for larger designs, and a tcl-based UserWare API. SpiceVision PRO fits into any EDA environment where SPICE design files are used to verify circuit behavior. It produces transistor-level schematics from complex SPICE descriptions to help visualize parasitic effects. SpiceVision PRO generates schematics from pure SPICE connectivity information using Concept's
transistor-level schematic engine.

Cypress Semiconductor Corp. announced that it is sampling the POSIC2G framer (CY7C9537), a 2.5 Gbps channelized SONET/SDH framer with Generic Framing Procedure (GFP). POSIC2G provides support for both resilient packet ring (RPR) protocol operation at OC-48/STM-16 (2.5 Gbps) rates and solutions for existing data transport infrastructure, as well as efficient RPR mapping with GFP. RPR technology is designed for efficient transport of packet data over a ring topology. This technology simultaneously supports traditional carrier-class features such as performance monitoring, resiliency, and data restoration, as well as newer services for packet data and latency sensitive traffic.

HP introduced two new servers, the HP ProLiant DL740 and the second-generation HP ProLiant DL760. The servers include the HP F8 chipset, hot-plug RAID memory, and HP ProLiant Essentials management software. The company says the servers are appropriate platforms for high-performance, database, and business applications. The HP F8 chipset is based on a symmetric multiprocessing architecture and combines PCI-X I/O technology, Gigabit Ethernet, Ultra3 SCSI, and the Intel Xeon processor MP. The company also says the ProLiant servers offer fault tolerance and availability, which are important, as Microsoft Windows Server 2003 and Linux increase addressable memory.

Also from HP - The company has added two PCs to the HP Pavilion desktop line - the HP Pavilion 754n and 764n, which includes a DVD+R/+RW and a six-in-one media card reader, for under $1000. The six-in-one media card reader, positioned on the front of the PC, allows users to transfer data from all common flash media formats. Additionally, the 764n includes a NVIDIA GeForce MX 440 graphics card and 128 MB DDR graphics memory.

Again from HP - The company announced the HP super-scalable processor chipset sx1000 and the HP mx2 dual processor module using Intel Itanium 2 processors. The company says the products enable enterprise customers to keep IT costs down by scaling performance in existing servers - the chipset and module scale the size of HP servers using Itanium 2 processors and double the number of future Itanium 2 processors that can be used in an HP server.

Infineon Technologies AG announced the availability of a family of unbuffered DIMMs (dual-in-line memory modules) in 128MB, 256MB and 512MB densities. Based on 256Mb (megabit) Double-Data-Rate 400 Mbps (DDR400) memory, the modules are compliant with Intel specifications and designed to meet the requirements of the proposed JEDEC PC3200 3.2 GBps (gigabyte-per-second) bandwidth specification for use in the main memory of high-performance desktop PCs and workstations. The PC3200 DIMMs and memory chips are immediately available, and are produced in 0.14-micron process technologies and in production volume at Infineon's 300mm and 200mm DRAM fab cluster.

InnoLogic Systems, Inc. announced that STMicroelectronics is using InnoLogic's ESP-CV to eliminate functional bugs in its embedded memories that are included in product lines in telecom and data communications, consumer and automotive electronics. ESP-CV verifies the functional equivalency of full custom designs across various levels of abstraction. STMicroelectronics reports its designers were able to find and fix functional bugs and streamline the verification of compiler generated embedded SRAM's, ROM's and DRAM's using the tool.

Intel Corp. announced plans to convert Fab 12, a 200mm wafer fab in Chandler, AZ, to a 300mm wafer fab. The conversion project, estimated to cost $2 billion, will begin in the first half of 2004 with production scheduled to begin in late 2005. The converted fab will start up production on 65-nanometer wafers. When completed, the converted Fab 12 will become Intel's fifth 300mm facility. The company currently has two 300mm fabs in operation - one in Hillsboro, OR, and one in Rio Rancho, NM. Two other 300mm facilities are under construction. One in Oregon will begin operations later this year, and a facility currently under construction in Ireland is scheduled to begin operations in
the first half of 2004. Additionally, the company announced plans to sell 524 acres of land in Forth Worth, TX. The land was purchased in 1997 as part of a planned manufacturing facility. However, changes in manufacturing technology and current construction projects at existing Intel sites mean the property is no longer part of the company's future plans.

Mentor Graphics Corp. announced a PCI Express configurable controller core for development of subsystems supporting the PCI Express serial interconnect technology. To help validate functional compliance, Mentor is also providing an in-circuit emulation PCI Express verification tool, based on the VStation and Celaro emulation systems. The company says the PCI Express roadmap includes full support for the specification including endpoint, legacy endpoint, bridges, switch, advanced switches, and root complex configurations. Configurable options include the number of virtual channels, the number of lanes (up to 32) and links per port (up to 32) and the maximum payload size. Flow control
is provided for different types of traffic. The first IP (intellectual property) release will be capable of supporting PCI Express Endpoints and bridges from one to four lanes in width.

In related news -- Mentor Graphics and Altera Corp. announced a reference design for the development of applications based on PCI Express serial interconnect technology. The design includes a configurable PCI Express IP core and in-circuit emulation verification from Mentor Graphics and a Stratix-based PCI card from Altera. The Mentor Graphics board illustrates a PCI-to-PCI Express Bridge application running at full speed in an Altera Stratix PLD-based PCI card. The system is designed to connect to Mentor Graphics' VStation hardware emulation platform via a parallel interface, and implements a back-to-back bridge that converts PCI through to PCI Express Protocol and back to

Also from Mentor - The company announced that fully supported Calibre DRC (design rule check) rule files are now available for 90-nanometer technologies from UMC. Calibre has been UMC's standard for physical verification since 1998. UMC is a member of Mentor's Design for Manufacture (DFM) Silicon Partners Program, which guarantees mutual customers a set of rule files for Calibre DRC, Calibre LVS, and Calibre xRC. Rule files can be downloaded from UMC's website.

National Semiconductor Corp. introduced a system solution for GSM/GPRS handsets, which integrates analog and wireless capabilities including audio, power management, Bluetooth connectivity, imaging interface, baseband, and RF into a module and chipset platform for mobile phone manufacturers. The integrated chipset is customizable to address end-user specifications including ODMs and OEMs needing a GSM/FPRS engine. Both the chipset and module come with full development kits. The LMX3888 module includes an on-chip polyphonic ringer, speakerphone, stereo MP3 capabilities, an integrated Bluetooth Link Manager, USB, CMOS camera interface, SD/MMC interface, voice recognition, voice memo,
hands-free speakerphone, EMS and MMS. The chipset and module are currently sampling to select customers and will be available for general sampling in June 2003.

Open Core Protocol International Partnership (OCP-IP) announced that TNI-Valiosys has joined the organization as a Sponsor Member, thereby supporting OCP-IP's efforts to create a common standard for IP core interfaces to facilitate plug-and-play SoC (system-on-chip) design. The company says that adoption of an industry-standard interface will permit TNI-Valiosys to make its formal solution available to more designers and increase IP reuse.

Pericom Semiconductor Corp. announced a new family of low voltage differential signaling (LVDS) devices that support high-speed data transfer. LVDS is used in applications requiring high-speed data transfer, low power, or low EMI. The seven new devices support Pericom's portfolio of low voltage differential signaling products. LVDS is a differential standard using two signal lines to communicate data or clock signals over PCB traces or balanced cables such that noise is decreased on the line through common-mode rejection. Since there is less noise than a single-ended method of transmission, the signal can be dropped to the millivolt level. The small signal swings allow for faster
data rates because of the short rise times. Pericom's new LVDS devices are available now for general sampling.

Rambus Inc. introduced its parallel bus logic interface family, code-named Redwood, for high volume, low-cost systems. The Redwood family of products includes a per pin data rate of 400MHz to 6.4GHz and is optimized for low latency and low power parallel bus applications. Redwood can be backwards compatible with existing LVDS-based standards such as HyperTransport, SPI-4, and RapidIO, and therefore, offers a range of frequency and voltage support. Elements integrated into the Redwood technology include low-voltage differential signaling, FlexPhase timing calibration circuit technology, and dynamic current and termination capabilities. The Redwood family of parallel bus logic
interfaces is available now for licensing.

Synplicity, Inc. announced it has enhanced its Amplify Physical Optimizer software for physical synthesis of FPGA designers, by extending its MultiPoint technology and interactive timing analysis applicable to system-on-a-programmable-chip (SOPC) devices. Additionally, Synplicity now offers support for Altera's Stratix GX and Cyclone devices, and has enhanced its support for the Xilinx Virtex II-Pro devices.

Texas Instruments Inc. announced four new GSM/GPRS chipsets as additions to the TCS family of chipsets. The latest additions to TI's GSM/GPRS chipset family include the TCS2600, TCS2620, TCS2200, and TCS2010 with low power consumption, reduced board space, and increased component-level integration. The company says the new chipsets are capable of supporting various applications including secure m-commerce, multimedia games and entertainment, location-based services, streaming media, accelerated Java processing, web browsing, and enhanced 2D graphics. The TCS2600 includes the OMAP730 smartphone processor and a Class 12 GPRS modem with an ARM926 general- purpose processing core. The
TCS2620 chipset includes the OMAP732 processor, plus up to 256 Mb of stacked mobile SDRAM. The two other new chipsets, the TCS2200 and the TCS2010, are based on the same architecture as TI's TCS2100, a Class 12 GSM/GPRS chipset.
All of the new TCS chipsets will be supported by development tools and handset reference designs. Sampling and production availability of the 4 chipsets will roll out across 2003.

TNI-Valiosys - The company announced the first release of the forthcoming OCP2.0 Formal Compliance Checks (OCP2.0 FCC) library of assertions to be used in conjunction with the company's static property checking tool, imPROVE-HDL. The company is contributing two one-year subscription licenses of the OCP2.0 FCC library free of charge to all OCP-IP Governing Steering Committee members.

Toshiba America Electronic Components, Inc. (TAEC) announced the introduction of the first products in a new series of high-speed 8-bit microcontrollers suitable for portable battery-powered applications. The TMP86FM48U and TMP86FM48F are capable of operating at 8 MHz and 1.8 V. The TMP86FM48U/F has 512 bytes of built-in data EEPROM and incorporates Flash memory that can be programmed via the Universal Asynchronous Receiver Transmitter (UART), making it possible to program and reprogram the device after the chip has been mounted on a user board. TAEC says that in recent years, the portable applications market has seen a trend toward small-scale, diversified production, which has
increased demand for microcontrollers with built-in Flash memory and performance comparable to their mask ROM counterparts. Samples are scheduled to be available in March 2003 and volume production is slated to begin in May 2003.

Xilinx Inc. announced a web-portal addition to the Xilinx eSP web portal to accelerate development of wireless applications. The portal provides resources for system designers and includes specific reference designs to IP resulting from collaboration in the areas of cellular networks, fixed broadband wireless, and wireless LANs. The site also provides wireless technology tutorials, market overviews, system block diagrams, glossaries, and a directory of wireless experts.

Also from Xilinx - The company and Jungo Software Technologies, Inc. announced that Xilinx will include a 30-day evaluation version of Jungo's driver development software - WinDriver, KernelDriver, and Hardware Debugger - in its Real-PCI 64/66 design kit. Jungo's driver development tools include graphical user mode development environments, APIs specific to Xilinx PCI technology-based cores, samples, and diagnostic and debug utilities for device driver development.

Coming soon to a theater near you

electronicChina - Held in conjunction with PCIM China's International Conference for Power Electronics, Intelligent Motion, and Power Quality, and SEMICON China - this is Messe München International's second annual international trade fair in Shanghai and showcases components, assembly, electronics production, and photonics technology. It will be taking place from March 12th to 14th at the Shanghai New International Expo Centre (SNIEC), and will include the electronicChina Forum addressing “Global Trends and Future Technological Challenges in Mobile Communication.” Last year's trade show attracted 284 exhibitors from 17 countries and had more than 15,000

ISPC and GSPx - This is GTC's (Global Technology Conferences) first annual International Signal Processing Conference and Global Signal Processing Expo and will be running March 31st through April 3rd in Dallas, TX. Organizers say the event is “addressing the needs of the industry and academia for an event presenting signal processing enabled applications.” They report that 400 presentations have been selected from 560 submissions representing over 40 countries. And with an eye to the future, Conference Chair Dr. Amnon Aliphas says, “This venue offers a unique opportunity to prepare yourself for the economic rebound.”


CoWare has named Dr. Heinrich Meyr as Chief Scientist reporting to CoWare President and CEO Alan Naumann. Dr Meyr, co-founder of LISATek Inc. - recently acquired by CoWare - has also been named to the CoWare Board of Directors and will lead its Technical Advisory Board. Currently, Meyr is head of the Institute for Integrated Signal Processing Systems (ISS) at the Aachen University of Technology in Germany. Previously, he founded CADIS GmbH and introduced COSSAP, a tool for the communications industry. CADIS was acquired in 1993 by Synopsys, Inc. Meyr has published numerous IEEE papers, is a Fellow of the IEEE, a recipient of the Vodafone Prize for contributions to wireless
communications, and holds several patents. Additionally, he has served as Vice President for International Affairs of the IEEE Communications Society. Meyr received an M.S. and Ph.D. from ETH in Zurich, Switzerland, and spent 12+ years in industry research and management positions before accepting a professorship in Electrical Engineering at RWTH Aachen in 1977.

In the category of ...

Three scoops and a banana split

The 'scoop' is a time-honored tradition in journalism - even in technical journalism - but in today's economic climate where fewer and fewer editorial platforms exist, a situation has developed where the 800-pound publishing gorilla in our midst expects to have that scoop the first time, every time, without fail. Editors know it. PR and Marketing folks know it. Advertisers know it.

Philosophically speaking, it's not really clear what value a 'scoop' has in technical journalism. Say, for instance, your company is introducing a new software or hardware product - or the latest release - does that product only have value if the story is 'broken' by the 800-pound gorilla? Do users find less value-add in a new product because a story about a release was inadvertently 'scooped' by a press entity other than the Big Guy Himself? Say somebody forgets to read the 800-pound gorilla in one particular week and hears about a new product, or new CEO, or acquisition from an alternate source - is that news no longer valid? Is it no longer relevant to the technical landscape?

Apparently so. In fact, you've missed one of life's minor thrills if you've never witnessed the palpable hysteria that develops when a mistake occurs and the 800-pound gorilla doesn't get to run a story first. Apparently that Guy is one Scary Dude. Apparently, he doesn't forgive, doesn't forget - and once offended, no apology is ever sufficient to appease him. By all reports, there aren't enough bananas on the tree to placate him.

So just in case you didn't already know to respect the long-suffering folks in Marketing and PR, you should fix that immediately. They're involved in a pretty dangerous game - especially with all of those banana peels lying around!

Courteous-Engineer-as-Copy-Editor Commendation

A special award goes to Simon Bates, Principal Staff Engineer for the IP Transfer Team at ARM Ltd., who writes: “A great newsletter this week - captures the surreal nature of modern life. Minor point - isn't Lightspeed using Sequence to 'reduce' rather than 'increase' design runtimes?”

He's right - here's the correct version of the news item:

SANTA CLARA, Calif.- (BUSINESS WIRE) - Feb. 11, 2003 - Sequence Design's ShowTime, the advanced nanometer analysis tool for SoC timing and signal integrity, and Columbus-Turbo for high-speed extraction, are helping Lightspeed Semiconductor achieve breakthrough design runtimes according to Michael Sydow, Lightspeed vice president of marketing and applications engineering.

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-- Peggy Aycinena, EDACafe.com Contributing Editor.