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March 10, 2003
Patent Law 101
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Steve Beyer has been mountain climbing in Nepal, backpacking in New Zealand, and has lived and worked in Japan. He's an avid cyclist and has never been known to shy away from a pick-up game of basketball, no matter how tough the opponent. But all of this pales in comparison to his principle adventure in life - Patent Law.

Beyer was half-way through graduate school at Stanford, when it occurred to him that one way he could leverage his engineering and his interest in writing was to go to law school. He set his sights on doing just that, after completing his MSME, and promised himself that, no matter what, he'd never go into patent law.

Predictably, the first job he landed out of graduate school - the one that was to support him through law school - was a job at the U.S. Patent Office. There he learned the ropes (and tedium) of poring over patent applications and working with those who come hoping to certify that their idea is a patentable one.

Beyer's work in the Patent Office was educational, but hardly inspirational, so when he had an opportunity to go work at a law firm, while still working his way through law school, he jumped at the chance. It was a patent law firm and the rest is history.

Today, despite all of his initial intentions to the contrary, Steve Beyer is a patent attorney and partner in Beyer Weaver & Thomas, LLP - an intellectual property law firm with several offices in Northern California. More importantly, for the legal novice with an interest in the subject, Beyer is a patient and willing instructor. He really likes this stuff.

It starts with an idea

Beyer says the patent process always starts with an idea, and he says you can try to patent just about anything. However, in order to successfully defend a patent to the U.S. Patent Office you need to prove that:

- The idea is a novel one.

- It's different from anything else that existed before.

- It's not obvious to a person with "ordinary skills in the area."

That all certainly seem straightforward enough, but according to Beyer it's a devilishly difficult task to actually prove that an idea meets these requirements. He says that whether you're trying to get a patent on a user interface, an operating system, a driver, or an optimization algorithm, to prove that your concept warrants a patent is very, very challenging - and can take anywhere from 10 months to 4 or 5 years from the initial filing of an application to the final awarding of the patent itself.

Anybody can work through the patent process on his or her own, Beyer says: "It's not rocket science." He says many inventors and innovators have successfully written and defended their own patent applications. Beyer doesn't discourage that type of thinking, but says that if someone does decide to spend the $12,000 to $18,000 required to hire a patent attorney to file a patent application (that includes several thousand dollars in application fees to the Patent Office), they'll get a lot of help for the money.

Such help includes assistance in researching the uniqueness of the idea - its "patentability" - and experience in documenting an idea to the level of detail required by the Patent Office - flow charts and block diagrams for software, or schematics for hardware, plus extensive descriptive narrative. Many patent attorneys, he says, have had experience themselves working in the Patent Office and understand the bureaucracy and mind-set of the people who work there.

Patent examiners who work in the Patent Office, Beyer says, usually have a technical degree relevant to the technology of the patents they're examining. However, he adds, frequently these individuals - though very dedicated to their craft - have never actually worked in the industry that's generating the patent applications that they handle. This isn't necessarily a problem, he says, just an important factor to keep in mind when working closely with the examiner who's been assigned to your application.

On the legal side, Beyer says that patent attorneys, particularly those in high-tech, have passed not just one, but two different types of Bar Exams - the well-known exam administered by each state which licenses an individual to practice "before the Bar," and the lesser know exam administered by the U.S. Patent Office which licenses an individual to "prosecute a patent" before the U.S. Patent Office. Additionally, you need a technical degree of some sort to be permitted to sit for the "Patent Bar" if you want to be licensed to prosecute patents in a technical area.

The term "prosecution" is a difficult one for the layman to get past in any discussion of patent law. In movies and TV, prosecutors are doggedly determined champions of law and order, trying to pin the "goods" on a miscreant of some sort or another. However, in the semantics of patent law, "prosecution" is the process by which a patent application is "defended" before the Patent Office.

Beyer says that 95-to-99 percent of all patent applications are turned down the first time around. That rejection then triggers several iterative rounds of additional documentation and communication between the applicant and the Patent Office - the process that can last upwards of 5 years - and this is termed "Patent Prosecution."

Beyer does not do "litigation" - the process whereby the party of the first part sues the party of the second part for "patent infringement." (Although he does serve occasionally as a consultant in patent litigation.) Anybody who lives and works in EDA probably knows more than they ever wanted to know about "litigation" - but, in any case, don't confuse "prosecution" and "litigation" when you're talking about patent law.

Is it a (venture) capital idea?

The legal fees associated with the prosecution phase of the patent process can run, again, from $10,000 to $20,000, according to Beyer. In other words, if you've hired a patent attorney to assist in the process, by the time your patent is actually granted you may have spent upwards of $30,000 to $50,000 on legal fees over all - only a small part of which are the actual fees required by the U.S. Patent Office.

Beyer says that if you're a small start-up, with perhaps only $500,000 in seed money, you're unlikely to see why you should shell out such a large percentage of that money for pricey legal fees just to pursue protection of your idea. In fact, you may even be ornery enough to think you don't need to file for patent protection at all for your idea or product. However, he says, there's more than just legal fees or a sense of empowerment hanging in the balance.

Beyer says, if you plan to seek out venture capitalists and angels to fund your technology start-up, you may find that though they are fascinated by your proposal, the very first thing they're going to ask is, "What have you done to protect your idea? Have you filed a patent application?" VCs are not usually willing to move forward, he says, and back your business plan if you have not laid down the requisite groundwork, "marked" your technical territory, and prepared to defend it from attack from competitors. So, as philosophically appealing as it may seem to go it alone without patent protection or burdensome legal fees, your first visit to a VC's office may radically change your point of

Meanwhile, say that you've filed the application, that you're enduring the prosecution phase, that your business is up and running based on your idea - what protection do you have from IP raiders while you're awaiting the final granting of your patent?

The answer is simple, Beyer says. "None. You have no protection. Until that patent is granted, you have no exclusive legal right to your idea or product." Which begs the question all over again - why go to all of this trouble if, during the early years, your start-up has no way to defend its technology. The answer is again simple. Just try to get initial funding, or subsequent rounds of funding, if you have not done due diligence in protecting your idea - and the investments of your backers.

A Ploy named Sue

Beyer says that when you finally receive your patent, you may be quite surprised about the wording in the document. He says a patent is never longer than a single sentence, but what a sentence it is! Beyer calls it "complete and utter gibberish" that thoroughly describes your intellectual property to an excruciating level of detail, and also describes exactly what nobody else can do with your IP.

A patent, he says, "doesn't give you the right to do anything - it only excludes others from doing something." This is a subtle distinction, Beyer adds, but one that is crucial at a later date when you decide to sue the party of the second part for patent infringement.

Which brings the discussion around to the patenting of a particular technology and de facto industry standards. Beyer says it's only the naïve who think that a company is pursuing "World Peace" by offering to let their technology be open sourced and declared an industry standard. In fact, he says, as soon as a company's IP becomes the standard, as soon as everybody else starts to produce product that is compliant with that standard, all of those compliance-seeking product producers now must pay royalties of some sort to the company who's technology as been 'chosen' as the standard - if that company owns a patent on the technology.

That may be obvious to most, but not to everyone, according to Beyer. A plethora of patent infringement law suits have arisen out of the situation where a company is designing product "compatible with industry standards" and either didn't know or "forgot" to seek out those who hold the patent on the standard - seek them out, that is, and offer to pay the appropriate royalties.

And there's even more to the labyrinthine world of patent holders, according to Beyer, and those are the strategies behind suit and counter-suit. He says, "In the semiconductor industry, everybody's infringing a bit on everybody else's patent." Beyer suggests a scenario where patent holders - and the corporate entities they work for - engage their competitors in a conversation that goes something like this:

"If you sue me, I'll sue you. I've got my pile of patents and you've got your pile of patents. I could sue you for patent infringement on X number of my patents, but I know you'd then turn around and sue me for patent infringement on Y number of your patents. So we'll just split the difference - I'll pay you some money for my infringements, and then you pay me some money for yours. Our lawyers and your lawyers will talk - they'll figure out the appropriate amounts. And then, we can continue to co-exist."

So, perhaps the naïve among us are right after all. All of this to-doing over patents - patents applications, legal fees, prosecutions, infringements, litigations - is indeed about "World Peace" if a patent, or a pile of patents, helps to promote "mutual respect" between fierce combatants vying for commercial dominance on the battlefield of high-tech competition.

Beyer confirms that there are two industries that are widely known for their litigious business practices. One, he says, is the medical devices industry. There are lots of small companies in that industry and it's fairly easy to tweak a minor feature on a device and prove that the result isn't infringing on someone else's patent.

Not surprisingly, the other industry notorious for its litigation is EDA. Per Beyer, it's fairly easy to tweak an algorithm just a tad, one that's buried deep in code, and prove that the "new" algorithm is sufficiently different from the "old" algorithm to disallow claims of patent infringement. Again, for anybody familiar with the EDA industry, this is not news.

Finally, it's clear from talking to Beyer that, from the hard-working examiner in the U.S. Patent Office to the savvy corporate executive who knows enough to threaten suit against somebody who's "nudging" up against a company's patent - there are lots of players in this game. It's an interesting game, a fascinating game to observe, and definitely not one for the faint of heart.

Industry News - Tools & IP

Agilent Technologies Inc. announced that BAE Systems has selected Agilent to provide a comprehensive package of RF and microwave EDA software, support, and on-site consulting. The company says its Advanced Design System (ADS) EDA software will help streamline design processes and improve productivity in BAE Systems' RF and microwave-module and MMIC (monolithic microwave integrated circuit) development for communications and aerospace and defense applications. BAE Systems designs, manufactures and supports military aircraft, surface ships, submarines, space systems, radar, avionics, communications, electronics, guided weapon systems, and other defense products.

Meanwhile, austriamicrosystems announced an enhanced product design kit (HIT-Kit) for linking austriamicrosystems RF process technologies with Agilent's RF Design Environment (RFDE). The company says the HIT-Kit will help speed the development of the Radio Frequency ICs used in wireless communication applications, including Bluetooth and mobile phones. HIT-Kit version 3.50 supports both the BiCMOS and the SiGe versions of the austriamicrosystems 0.35-micron technology node, which are modular extensions of the 0.35-micron mixed-signal CMOS baseline process licensed from TSMC.
Analog Design Automation, Inc. (ADA) announced the release of Creative Genius v2 and IP Explorer v2, which the company describes as high-capacity optimization tools for designers of analog, mixed-signal and custom ICs. Creative Genius v2 can optimize up to 200 devices across 60 environmental and manufacturing variations, with 30+ performance goals. IP Explorer v2 is a performance tradeoff analysis tool that allows multi-dimensional visualization of multiple circuit solutions, which allows analog designers to compare circuit performance.

Aptix Corp. announced a demonstration of the ARM926EJ-S microprocessor core PrimeXsys Platform on an Aptix Software Integration Station, running multimedia applications at multi-megahertz speeds with the AMBA Multi-layer AHB bus. The demonstration was developed by STMicroelectronics. The company says the demonstration reflects the use of Aptix technology with ST Microelectronics in their development of the recently introduced Nomadik chipsets for multimedia and wireless applications, based on the ARM PrimeXsys Platform. The PrimeXsys Platform is based around the ARM926EJ-S microprocessor core, which incorporates ARM Jazelle technology for Java acceleration, an AMBA multi-layer
AHB bus, and PrimeCell peripherals.

Artisan Components, Inc. and iRoC Technologies Corp. announced that iRoC has added support for Artisan's Process Perfect memory generators to its M-RoCKIT platform. Users of Artisan's memory generators, which automate the development of simulation and artwork views for single- and dual-port SRAMs and single- and two-port register files in SoC designs, can use the iRoC platform to design error correction code (ECC) while building hardened memory subsystems. Users specify details of required memory instances, and simulation and artwork views are generated. The M-RoCKIT architecture allows designers to protect memories within prescribed time, area, and power limits.

Axis Systems, Inc. announced XoC for hardware and software verification for embedded vertical markets. Initially, XoC will be targeted at the ARM-based SoC design market. XoC includes a co-verification debugger that helps create a common communication environment between hardware and software teams, and makes it possible for software designers to verify code functionality, before silicon, without having to learn hardware verification methodologies.

ARM - It's been a busy week for the company, starting with an announcement of the availability of the AMBA 2 Transfer-Layer SystemC interface specification, which is the result of a collaboration involving ARM, Synopsys, Inc., Cadence Design Systems and CoWare Inc. that is intended to deliver a standard for connecting system-level design IP endorsed by design tool and IP providers. The new methodology will allow designers to use IP built according to the interface specification for the exploration of AMBA methodology-based SoC architectures. In developing the specification, ARM says it has also received feedback from other partners including Mentor Graphics, Motorola,
Philips Semiconductor and Verisity to encourage broad industry endorsements for wide adoption of the new standard. Testimonials from Synopsys, Cadence, and CoWare accompanied the announcement.

Meanwhile, ARM and Synopsys, Inc. announced the availability of the ARM-Synopsys Reference Methodology as a part of all ARM synthesizable cores. The companies say that the methodology streamlines the process used by ARM Partners to port synthesizable ARM microprocessor cores to a specific technology, and to harden and model a core. The ARM11, ARM7, ARM9E, ARM10E, and ARM11 families have now been upgraded to include the new methodology. The ARM-Synopsys Reference Methodology includes Synopsys' RTL-to-GDSII tool flow.

Also from Synopsys - the company announced the addition of comprehensive test automation features for core-based designs to DFT Compiler SoCBIST, which is a component of the Galaxy Design Platform. The company says its SoC test solution comes with industry support from ARM, Agilent and STMicroelectronics and is based on the IEEE P1450.6 Core Test Language (CTL) standard. Additionally, Synopsys announced that the ARM-Synopsys Reference Methodology now includes Synopsys' SoC test solution for use with ARM IP core-based design flows.

ARM is also partnering with Cadence Design Systems, Inc. through a new five-year agreement "targeting design-chain optimization for their mutual customers." ARM is providing access to their IP to facilitate design and verification using Cadence tools on ARM core-based SoCs. Customers will be able to incorporate different ARM cores into Cadence's Incisive verification platform. The two companies say they are currently working on design chain interoperability via standardized models and validation suites for ARM's AMBA bus using the SystemC modeling language. Cadence is a member of ATAP (ARM Technology Access Program).

Meanwhile, from Cadence - the company announced enhancements to its CeltIC 4.1 signal integrity product, part of the Encounter IC design platform. The company says the enhanced software is faster than previous versions, and includes overshoot-undershoot glitch analysis for sub-130-nanometer technologies and a timing engine for timing window convergence. CeltIC 4.1 can also generate compatible timing windows for delay analysis with third-party tools.

Additionally, Cadence announced it has joined the FlexRay Consortium as a tool development member. The FlexRay Consortium is an organization formed in September 2000 to drive the adoption of an open standard for high-speed bus systems for distributed control applications in automobiles, such as x-by-wire.

CAST, Inc. announced two new IP cores implementing networking and bus standards, including the 1-Gigabit Ethernet media access controller (MAC-1G), and the USB version 2.0 function controller (CUSB2). The company says the new cores intend to provide a "cost-effective" method for designers to incorporate high-speed Ethernet or USB features into designs. The cores are designed for reuse, are delivered with verification tools and documentation, and are available in source form for ASIC synthesis or as netlists optimized for various programmable devices. The CUSB2 and MAC-1G will ship in April 2003 and May 2003 respectively.

ChipVision Design Systems, AG, announced a new version of ORINOCO, a design tool for optimizing chip-power consumption at the specification level. The company says the tools reduces power and decreases design time compared with RTL methods by working at the architectural level early on in the design process. In addition to existing design entry levels (using C/C++), ORINOCO will now support SystemC as well, via a SystemC user interface. A beta version of the new SystemC front-end was shown at DATE 2003 in Munich last week.

CoCreate Software, Inc. announced that Leviton Manufacturing Co. will deploy the company's OneSpace Collaboration to all of its U.S. and overseas manufacturing facilities. Leviton says it expects to reduce costs and streamline development by extending its current use of CoCreate technology to development and design staff throughout the company.

CoWare announced new versions of the LISATek EDGE processor designer, RIM software designer, and HUB system integrator tools, which include support optimized for integration with the CoWare N2C design environment. The new release also includes Memory Explorer, which lets system designers explore, analyze, and change the configuration of caches, buses, and memories during complied simulation runs. The compiled ISS model, "based on patent-pending Just-in-Time Cache Compiled Simulation technology," allows for the optimization of the memory subsystem. The company says the technology supports self-modifying code typical of an RTOS. The LISATek Macro Assembler was also announced and
features, which the company says are similar to a high-level programming language, including complex macros that can be called like processor instructions. CoWare recently acquired LISATek, Inc.

E*ECAD, Inc. announced that it has signed a distribution agreement with Solution-Soft Systems, Inc., whereby Solution-Soft will sell its GDSII compressor, gdzip, through E*ECAD's on-line sales channel using time-based licensing. Solution-Soft's gdzip compresses GDSII files to reduce transfer time by creating block-by-block checksums during compression to verify that the decompressed file is identical to the original.

HARDI Electronics AB announced version 2.1 of the HARDI ASIC Prototyping System (HAPS), for real-time speed and debugging. The new release allows for up to 8 million ASIC gates running at 200+ MHz on a single board. To accommodate larger designs, customers can also stack several boards. The HAPS ASIC prototyping platform includes FPGAs for implementing ASIC logic, connectors for adding IP-blocks, clock nets for high-speed, configurable connectivity for partitioning, and I/O connections. It is designed to support any ASIC, without modifications.

Novas Software, Inc. has extended its Verdi Behavior-Based Debug System to support "emerging assertion-based verification methods." The company says the new release integrates assertion languages and the results of assertion-based verification tools for the debug and analysis of complex ICs and SoC designs. Verdi enhancements are based on compiler and database extensions to Novas' Design Knowledge Architecture, and provide interoperability with third-party assertion-based verification tools.

Mentor Graphics Corp. announced a collaboration with Xilinx, Inc. and Thales Communications to develop a new FPGA verification flow to meet Thales' product development requirements. Xilinx will extend its existing EDA Partner Alliance agreement with Mentor Graphics, to include the FormalPro equivalence checking technology, ModelSim HDL simulation, and Precision Synthesis. The collaboration is intended to provide an integrated FPGA methodology to aid Thales in the development of next-generation military and aviation electronics.

Open Core Protocol International Partnership (OCP-IP), an industry association working on standards for IP core interfaces, announced the availability of the OCP Specification 2.0 release candidate. The specification includes a model for write transfers for precise end-to-end-responses, an enhanced burst model for both burst length and packet-style transfers, and support for user-defined in-band command data and response extensions which can be used to support features such as parity and Error Correcting Codes (ECC). The specification also makes provisions for "lite-weight" OCP interfaces with read-only/write-only/FIFO-style IP cores, as well as support for "lazy memory"

Sequence Design announced CoolTime technology as the basis for an instantaneous voltage-drop analysis tool that will be added to the company's electrical-integrity analysis tools for SoC design. The company says CoolTime analyzes power, voltage drop, timing, and signal integrity concurrently by examining the dynamic effects resulting from power-grid capacitance,
package inductance, and on-chip decoupling capacitors. In instantaneous mode, the tool runs at 2 million gates per hour. In static mode, it run at 25+ million gates per hour. The technology will be available commercially in Q2 2003.

Synopsys, Inc. and Applied Dynamics International (ADI) announced a real-time physical simulation environment for automotive design, which links Synopsys' Saber simulator with ADI's SIMsystem HiL equipment, for real-time verification of automotive system designs. The two companies say that, traditionally, automotive designers have had to build hardware prototypes for all of the mechanical, hydraulic, and electrical components used in a car's subsystems, and then combine these prototypes to simulate and verify the functionality of the entire car. Linking Synopsys' Saber simulation environment with ADI's SIMSystem HiL equipment is intended to replace the need for hardware
and, therefore, reduce the time required to simulate car subsystems, including the power train, the anti-lock braking systems, and the brake-by-wire, steer-by-wire, and throttle-by-wire systems.

Synplicity Inc. announced it has signed a joint development agreement with NEC Electronics Corp. to provide support for NEC's Instant Silicon Solution Platform (ISSP) ASIC devices. Under terms of the agreement, Synplicity will develop custom synthesis mapping technology for its Synplify ASIC software optimized for the ISSP devices. NEC Electronics has provided Synplicity with detailed information about its ISSP architecture, validated the Synplify software's performance, and will integrate the software into its overall OpenCAD design flow. NEC Electronics and its subsidiaries in North America and Europe will offer library support for the custom Synplify software to its ISSP
customers worldwide. As part of this joint agreement, Synplicity will train and work with NEC's field design centers to provide support. Additionally, Synplicity intends to develop future releases of the Synplify ASIC software in conjunction with NEC Electronics.

Telairity Semiconductor and Icinergy Software announced that Icinergy's SOCarchitect technology will be packaged with Telairity's high-performance ASIC design kit as the virtual prototyping environment for Telairity customers to perform physical design planning and timing estimation. The two companies collaborated to create a customized design solution that fits the specific needs of Telairity's ASIC design flow. Telairity is a fabless ASIC company providing tools, methodology, hard IP and services. Icinergy Software provides tools for complex IC and SoC design.

TransEDA PLC. announced a new release of VN-Property Checker and Analyzer, which now supports the Accellera Property Specification Language (PSL), formerly known as IBM Sugar. Udo Muerle, CEO at TransEDA said, "TransEDA is an active member of the Accellera committee and recognizes the tremendous value that this powerful and user-friendly industry standard language brings to our customers and the industry at large.
We have quickly adopted the new language into our R&D, and are proud to be the first EDA vendor to launch a property checking solution based on Accellera PSL." VN-Property is part of TransEDA's Verification Navigator integrated design verification environment, and combines formal verification and simulation.

Xilinx Inc. announced the availability of the Integrated Software Environment (ISE) version 5.2i and ChipScope Pro 5.2i. The company says the new "ASIC-strength" design tools will help with timing closure and will reduce design costs and time spent in the design flow. The company also says ISE 5.2i will help customers begin designing with the company's
next-generation MultiGigabit serial I/O transceivers and 90-nanometer FPGAs. All configurations of ISE 5.2i include various design options that can augment existing programmable design flows and fit specific methodologies.

Industry News - Devices & Fabs

Amkor Technology, Inc. announced the sale of its wafer fabrication services business to Anam Semiconductor, Inc. (ASI) for $62 million. The company says it has obtained releases from numerous customers of the wafer fabrication business regarding Amkor's contractual obligation to perform wafer fabrication services subsequent to the transfer of the business to ASI.

Infineon Technologies announced the VDSL5100 chip set, which is a QAM-based chip set for very high-bit rate DSL (VDSL) applications that have a total aggregate data rate of greater than 100 Mbps, including Ethernet over VDSL and ATM over VDSL. (Quadrature Amplitude Modulation (QAM)) combines two amplitude-modulated signals into a single channel to double the effective bandwidth.) The VDSL5100 provides asymmetric data-rates of 70 Mbps downstream/40 Mbps upstream and symmetric data-rates of 50/50 Mbps over single-pair copper wires, to allow service providers to offer a broader range of high-bandwidth content to subscribers, including movies, high-definition television and gaming.
The VDSL5100 is designed to support universal line card designs, with software programmability, which means equipment manufacturers can use a single configuration to support regional Band Plan requirements and various transport protocols in switches and DSLAM line-cards, as well as customer premise equipment (CPE).

Also from Infineon - The company announced that its subsidiary, Infineon Technologies North America Corp., has agreed to acquire the assets of MorphICs Technology Inc. to strengthen its position in the 3G sector and enlarge its IP portfolio for multi-standard wireless design with programmable chips for digital baseband signal processing. The terms and conditions of the acquisition were not disclosed. MorphICs is a privately held fabless semiconductor company that develops configurable digital baseband circuits for terminal devices and basestations for 3G wireless communications.

LSI Logic Corp. announced availability of seven user-configurable RapidChip slices, which will be additions to the RapidChip design platform. The slices will provide standards-compliant serializer/deserializer (SerDes) technology, an ARM processor, and logic and memory integration capabilities. The slices are intended for the communications, storage and consumer markets. The company says that the new products will attempt to close the market gap between FPGAs and cell-based ASICs by offering density, performance, and power characteristics found in cell-based ASICs along with lower development costs associated with FPGAs.

Micron Technology, Inc. announced the availability of 1.3 megapixel (MI-1300) low-power CMOS progressive-scan active-pixel image sensors designed for digital still cameras, digital video cameras, and PC cameras. The company says the new sensors use the company's DRAM CMOS process technology to give charged coupled device (CCD) level image quality along with the benefits of CMOS sensor technology.

Motorola, Inc., Semiconductor Products Sector, announced it has expanded the line of integrated controller area network (CAN) microcontrollers (MCUs) that include on-chip flash memory. The 68HC908GZ8 and 68HC908GZ16 MCUs are additions to the 8-bit HC08 family and are intended for space-limited applications. The MCUs are available in 32- and 48-pin packages. The company says that CAN MCUs are used in industrial automation and motor control, and that upwards of 150 million network devices are connected with this protocol. A key CAN features is the ability to allow one component of a distributed network to talk to another, with minimal reliance on a central computer, which makes the
technology useful in applications such as packaging machinery, agricultural equipment, and medical devices.

National Semiconductor introduced what the company says are "the industry's most powerful boost regulators in a tiny package." The two new products are part of National's new family of high-frequency SOT-23 regulators and combine current-mode control, sub-miniature packaging, and high switching frequency,
and are based on the company's analog bipolar CMOS DMOS 150 process. The two converters, the LM2731 and LM2733, operate at a 1.6 MHz switching frequency and are housed in a SOT23, 5-pin package. Both the LM2731 and LM2733 are currently shipping.

TDK U.S.A. Corp., a subsidiary of TDK Corp., announced that it has entered into an agreement and plan of merger with Innoveta Technologies, Inc. and "certain other parties" named in the merger agreement. Subject to conditions specified in the agreement, TDK USA has agreed to acquire 100% ownership of Innoveta by means of a merger of TDK USA's wholly owned subsidiary with and into Innoveta. Upon completion of the merger, Innoveta will become a wholly owned subsidiary of TDK USA and will be renamed TDK Innoveta Inc.

Texas Instruments Incorporated (TI) announced a new DSP-based digital media processor, and a corresponding suite of support software and development tools. The new processor is intended for digital still cameras in the 3-5 megapixel range, digital video cameras, and portable multimedia products, and will provide fast shot-to-shot image capture and single-channel MPEG-4 encoding at 30 frames-per-second (fps) for VGA resolution video. The TMS320DM270 (DM270) integrates the TMS320C54x DSP, the ARM7TDMI RISC processor, and video and imaging coprocessors. Software support will be available for all major video, imaging, audio, and voice compression standards.

Toshiba Corp. announced what the company says is the world's first prototype of a small form factor direct methanol fuel cell (DMFC) for portable PCs, which Toshiba says is a clean energy source with the potential to end reliance on rechargeable batteries. The new fuel cell currently yields an average output of 12W and maximum output of 20W, and offers up to five hours of operation using a single cartridge of fuel. The fuel cell provides instant power supply and improves operating times with replaceable methanol cartridges.

Coming soon to a theater near you

ISQED Panels - The Dan Rather, Peter Jennings, and Tom Brokaw of the EDA world will be moderating three panels at the upcoming International Symposium on the Quality of Electronic Design, running from March 24th to 26th at the DoubleTree Inn in San Jose, CA. Tets Maniwa's panelists will discuss the brooding issue of "Hidden Quality, Crouching Customer - How much does the Quality of EDA Tools Impact Electronic Design?" Steve Ohr's group will tackle "Is Quality a Design Constraint for Sub-100-nanometer Designs?" Richard Goering's roundtable will touch on "IC & Package Co-Design Challenges." Industry observers say that wagers are running heavily in favor of "Lots, Yes, and Many" as the
conclusions that will be reached by participants in the respective panels. Meanwhile, conference organizers report that ISQED keynoters will include Bob Payne from Philips Semiconductor, Susumu Kohyama from Toshiba, Ted Vucurevich from Cadence, Rajeev Madhavan from Magma, and Michael Reinhardt from RUBICAD. (

IEC NanoEngineering TecForum Webcasts - The International Engineering Consortium is webcasting the archived nanotechnology presentations from DesignCon 2003. There are six 45-minute talks available on-line, which focus on the current state of nanotechnology, its impact on university curricula, current and future applications of research in the area, and various implications for practicing engineers. The presentations were made in conjunction with the Electrical and Computer Engineering Department Heads Association (ECEDHA), with support from the National Science Foundation, and are definitely worth your time if you want to bring yourself up to speed on various aspects of the
technology. (

Introduction to EDA - Everybody's favorite spokesperson for interoperability, Karen Bartleson, will be presenting a course entitled - "Introduction to EDA for Non-technical
Professionals" at the Embassy Suites in Santa Clara, CA, on April 14th. The full-day course, sponsored by Semitracks, Inc., is based on a workshop Bartleson conducted last year at DAC 2002. It's intended for non-technical folks who would like to know more about the semiconductor and EDA industries. If you've ever been lucky enough to sit in on one of Bartleson's seminars, you know your time will be well spent if you can make it to the upcoming event in April. (

Silicon Valley Web Guild - "Virtual Trade Shows: One Answer to Today's Business Malaise" will be the subject of a presentation by IBSystems' President David Heller at the March 20th meeting. The forum is open to the general public and is being sponsored by the Guild's eBusiness Perspectives special interest group. The meeting is being hosted by Cypress Semiconductor in San Jose, CA. (


CoWare announced that Uri Mayer, formerly President and CEO of LISATek, Inc. - recently acquired by CoWare - had been named to the newly created post of Vice President for European Field Operations. Mayer reports to Peter Richards, Vice President, Worldwide Field Operations at CoWare. Mayer will oversee CoWare's European market as the company establishes CoWare GmbH in Munich, Germany. Mayer has 20+ years' experience in the ASIC and EDA industries. Prior to his position at LISATek, he was Vice President of Worldwide Business Development for Synopsys, where he also served as Managing Director of Synopsys GmbH. Mayer has an MSEE from the Technical University of Munich.

DSP Group announced it has located operations on the Alba Campus in "Silicon Glen" in Livingston, Scotland. The company says a major factor in its decision to locate its European headquarters in Scotland was the availability of engineering expertise within the Alba Campus community. Alba Campus is a 100-acre site in Livingston specifically aimed at providing "purpose-built" accommodations to attract companies in the electronics design sector to Scotland).

Electronics Workbench announced the appointment of Ian Suttie to the position of Vice President of Sales and Marketing. Suttie will be responsible for developing global sales and marketing strategies to support the company's position in the PCB design market. Before joining Electronics Workbench, Suttie was COO at PCI, President and CEO of Waterloo Maple, Inc., and President of SST. Suttie has also served as a director of several private companies, industry associations, and standards organizations. He has 15+ years' experience in sales, marketing, and executive management. Suttie holds an MBA from Wilfrid Laurier University, a BSE from the University of Western Ontario, and is a
registered professional engineer.

The Microelectronics Imaging & Analysis Centre (MIAC), a silicon chip "microsurgery unit," announced it has received a £200,000 investment from the Scottish Enterprise to upgrade its facilities. Part of a three-stage upgrading program, immediate improvements will include the introduction of a new technique to allow the repair of copper-based ICs. The new technology capability will mean that this will be the only commercially operated facility in Europe able to carry out the repair of copper interconnected devices. MIAC offers electronic design companies facilities to analyze and repair prototype designs quickly and without the need for a full redesign. These techniques are
referred to as 'chip microsurgery' and involve rewiring the chip circuitry.

In the category of ...

Pending News of War and Peace

This newsletter is usually wrapped up mid-day Friday, prior to the Monday morning e-mail blast that pushes it out to subscribers. The current, painfully complex international situation is sufficiently charged, however, that anything could happen between a Friday afternoon and a Monday morning. If this newsletter doesn't reflect high-profile news stories from the weekend, it's because it can't - it's 'gone to press' too early to reflect weekend news.

In normal times, that wouldn't be a problem - international news is not within the scope of this newsletter. But it's hard to call these past few weeks and months 'normal times.' Last week's EDA, IP, and semiconductor news might appear eerily insignificant on a Monday, if seen against a backdrop of late-breaking international developments.

Clearly, what goes on around this globe has had, and will continue to have, an impact on all of us - no matter where we live or within which faction we find ourselves in the midst of this n-dimensional mess. The ebb and flow of human history is important and none of us live or work in a vacuum. But, although the news items in this newsletter are hardly on par with declarations of war or peace, they do reflect the continuing efforts of people trying to push innovation - and best their competitors - in a process that is also a part of the ebb and flow of human experience.

No matter what - most people will continue to try to work, to create, to support their families, to be responsible citizens within their own societies, and to bear up to the best of their abilities even within the most difficult of situations. Carpe diem.

You can find the full EDACafe event calendar here.

To read more news, click here.

-- Peggy Aycinena, EDACafe.com Contributing Editor.