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May 05, 2003
Design to Silicon
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor


by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Several weeks ago, on April 8th to be exact, the Fabless Semiconductor Association (FSA) hosted an all day meeting in Santa Clara, CA - "The FSA Smart Fabless Models I & II Design Productivity and Outsourcing" seminar. Over a 100 people showed up and learned lots over the course of the day. Now "learned lots" is a relative phrase, as there's a fine distinction between absorbing facts and absorbing impressions. Presuming that "learned lots" means absorbing impressions, the FSA event was a very educational day.


The second panel of the morning included Gary Montgomery, Director of Product Marketing at MIPS, Tom Riordan, Vice President and General Manager for the Microprocessor Products Division at PMC-Sierra, and Aurangzeb Khan, Corporate Vice President and General Manager of the Cadence Design Foundry portion of Cadence Design Systems.


The three men addressed a variety of questions grouped under the rather large subject umbrella of "Design to Silicon" and as they each represented a distinct industry niche - MIPS in IP, PMC-Sierra in fabless semiconductor, and Cadence in EDA - Montgomery, Riordan, and Khan were able to compose a fast-paced overview of Design to Silicon, agreeing to agree on most of the larger issues.


To clarify the discussion, they started by defining System on a Chip. MIPS' Montgomery said, "It's an IC with a compute engine." PMC's Riordan said, "It's a chip with system-level integration including a microprocessor, custom logic, memory, and IP. It's a true system and requires that an operating system be included." Cadence's Khan agreed and referenced the Dataquest definition, "An SoC is a chip with system-level integration."


The definition was important to frame the follow-on question: "What percentage of current design starts and products coming off the line today are SoCs?"


MIPS' Montgomery said, "Of the ASICs our customers are producing today, 50% are SoCs. That number will increase to 75% within 3 years." PMC-Sierra's Riordan said, "[Approximately] 3 out of 30 projects have been SoCs over the last 2 years." Cadence's Khan said, "Of the 100 designs we see per year, two-thirds of them are SoCs." Clearly the numbers reflect the industry niche within which each man operates.


What about the availability of quality, commercial IP and the related commitment within corporations to design reuse methodologies needed to accomplish these complex designs? Not surprisingly, MIPS was all over that one. Montgomery said that quality IP is very available and definitely a reality today.


Riordan, however, said that PMC is not using microprocessor IP or analog IP. "We tend not to use IP from external sources. We're always working on bleeding-edge designs, and synthesizable cores often present high jitter issues." He added that in his own personal experience, internally developed IP is not really ideal either, never adequately documented by the development team, potential reuse within the company often compromised by lack of follow through. Cadence's Khan countered by saying that a company's commitment to design reuse was totally dependent on attitudes coming down from management.


That dovetailed with the next question on the state of affairs with regards to design collaboration across companies and continents - by all reports, the stuff of reality when it comes to SoC project development.


PMC's Riordan said he regularly deals with projects that span two continents and multiple time zones, and makes the whole thing work by using off-the-shelf design management tools. MIPS' Montgomery said, "Ten years ago, I was working on a project where the DSP portion of the design was done in Israel, the microprocessor was done in the States, and the project integration was done elsewhere in the States. It was an absolute nightmare! I've never forgotten that. It's much better today with the tools available."


Good news there, but what about system-level design and the languages needed to facilitate these huge designs? Cadence's Khan said the manual hand-off between software and hardware portions of big projects has necessitated the development and use of system-level languages, but transaction-level modeling, hardware acceleration for emulation, accelerations suites, and partitioning designs into manageable blocks is also crucial to the strategy. Khan added, verification continues to be the biggest stickler.


Meanwhile, popular wisdom tells us all that verification only gets "sticklier" as the process technologies gets smaller and sexier. MIPS' Montgomery said that shrinking geometries are linked to product volume - or should be, via a consideration of the economics involved. A company should defend the move to smaller process technologies and higher integration by demonstrating that increased production volume will support the move. He asked rhetorically, "When does a transistor becomes cheap? A higher degree of integration must be justified by a subsequent lower cost per transistor over a two year period."


PMC's Riordan was unforgiving in his thumbnail sketch of recent process technology migrations: "Every other technology migration [over the last few years] has been a disaster. We got to 0.25 microns late. Things went wrong. The tools weren't ready from the vendors. Then we went to 0.18 microns and it proved to be an absolutely magnificent technology. Even today, you could start whole new companies based on 0.18-micron technology. Then we moved to 0.13 microns. Again, it was an absolute disaster! Major vendors went to Cu and low-k [dielectric materials] at the same time. We needed to handle [additional] data because there were lots of extra vias. [Now we're looking] at 90 nanometers and 0.13
microns at the same time. 0.13 has been so late [coming on line], 90 nanometers [is a big question mark]."


Cadence's Khan was succinct: "You've definitely got metrology issues, plus design issues at 90 nanometers."


PMC's Riordan continued: "We need to manage these issues to get the larger design done. We [definitely] stubbed our toes in moving from 0.18 to 0.13-micron technologies. And 90 nanometers is creating a lot of anxiety, the biggest problem being leakage - along with speed, power, and reliability. And, we [also] need to find the best [design] practices to [address] areas of weakness in chip packaging and board design, where we're transmitting signals in the GHz range across the board. And, then there's the flip chip issues."


With so many problems, how is the industry managing the human resources needed to conquer it all? MIPS' Montgomery said, "We're trying to integrate analog into a digital arena. There's [clearly] a shortage of mixed-signal expertise, but there are still large numbers of [capable technologists] available." Not surprisingly, he added, "In the current situation, IP become [even more] important. We're starting to see more and more analog IP and we're seeing some help from the tool vendors there as well."


PMC's Riordan said, "We're making a large effort to keep our mixed-signal team together. And there are lots of [refugees] from the telecomm industry. We're starting to try to work with IP suppliers to avoid building things [from scratch]. But with only 500 pins on a chip [to access internal signals], there are large issues in mixed-signal design."


MIPS' Montgomery had a message for the EDA community: "Solve our verification problems. If we can have major blocks of a design commercially verified, [it will go a long way] to solving system-level problems."


Wrapping up, the panel laid out the Pain and the Potential.


MIPS' Montgomery said, "The cost of design is escalating. At 0.13 microns, mask costs are skyrocketing. We've got tens of millions of transistors [on-chip]. We've got big problems in Time to Market and Time in Market. Perhaps [we're beginning to see] products will last longer in the market if they come with re-programmability - where you can add new product shelf life through software. We've got to ask ourselves, 'What do you do to reach volume production successfully?' You extend an ASIC to an ASSP, and you have access to qualified and tested IP."


PMC's Riordan said, "Given that [level of] programmability, you'll have fewer designs, but you'll need more people [to develop the designs]. You'll have projects with more people and more [diverse] outcomes."


Cadence's Khan said, "We all want to go to 130 nanometers and beyond. How do we do these projects?" He answered his own question with a nod to his audience: "The fabless industry has always been good at partnering. We all need to specialize in building partnerships to move the entire industry forward."


Yep, lots to learn on a rainy day in Silicon Valley.




Industry News - Tools & IP


Altera Corp. introduced version 2.1 of its DSP Builder digital development tool that integrates The MathWorks' MATLAB and Simulink DSP development software with the Quartus II FPGA design environment. Version 2.1 allows FPGA co-processor development "in concert with" Altera's SOPC Builder system development tool.


Altium Ltd. is previewing a new design technology that brings software and hardware design into a single, integrated design environment. The company says the technology will allow engineers to use board-level design methodologies to design and implement entire digital systems onto an FPGA - including embedded microprocessor cores and the software that runs on them. The new technology permits engineers to put board designs straight into FPGAs, something the company calls a "Board-on-Chip" (BoC) design.


Altium's thinking goes like this: "Despite the emergence of high capacity, low cost FPGAs that offer the potential to be used as a platform for digital system design, there are currently significant cost and technology barriers facing engineers who wish to exploit this potential. Current tools are primarily HDL based and not well integrated with embedded software tools. Also, HDL-based IP cores are expensive and have complex licensing schemes. To date, these barriers have hindered the penetration of FPGAs as a platform solution for mainstream engineers. The new BoC technology will enable engineers to overcome these barriers and use familiar design methodologies to harness the power of FPGAs
as a design platform."


Altium says it has brought in technology from both its EDA and embedded products to produce the BoC design. The company's nVisage design capture and TASKING embedded software have been combined on the Design Explorer platform. The BoC system includes mixed schematic/VHDL design capture, integrated software development, processor core packs that combine pre-synthesized processor cores with matching compiler, simulator, and debugger, schematic component libraries containing pre-synthesized components, primitives and macro libraries for all Xilinx and Altera device families, virtual instruments such as logic analyzers and frequency counters that can be built into the design for
test purposes, and a BoC development board loaded with an FPGA that functions as a breadboard and allows implementation of the design from the engineers PC onto the FPGA.


The company says that an important benefit of the BoC technology is that it allows a more flexible approach to partitioning the design between hardware and software, and engineers can continue to choose between a hardware or software solution to any particular problem throughout the design process.


Ansoft Corp. released AnsoftLinks v2.5 to provide data export from the Mentor Graphics Board Station product to Ansoft design tools for use in PCB design. The companies say that PCB designers can use the additional features and capabilities of Ansoft's products while maintaining their existing Mentor Graphics design flows because of the new link between Mentor's Board Station and Ansoft's HFSS, SIwave, Spicelink and Ansoft Designer interfaces.


Cadence Design Systems, Inc. announced that Toshiba America Electronic Components, Inc. (TAEC) used the Cadence Encounter digital IC design platform with "nanometer synthesis technology" to design a 530 MHz (typical operating condition) synthesizable 64-bit dual-issue MIPS core. Cadence RTL Compiler synthesis, acquired through the Get2Chip purchase, and the NanoRoute Ultra signal integrity and timing-optimized router were used to produce the design - a multi-million gate, 130-nanometer, 7-layer metal CPU.


Emulation and Verification Engineering introduced a multi-board hardware verification system that the company says will handle up to 12 million ASIC-equivalent gates. Zero Bugs (ZeBu) is a hardware acceleration platform for verification of FPGA-based designs and associated embedded software. Up to eight ZeBu boards can to be connected together to accommodate large designs. The company also says that the system is less expensive, but operates at higher speeds, than what they describe as "high-end" emulation systems because multiple boards in multiple PCs are used collectively on one large design, or individually/concurrently on smaller designs.


Hier Design Inc. announced full support for Xilinx Inc.'s 90-nanometer Spartan FPGAs. The pre-release Hier software, which supports the Spartan-3 device, is being used at several beta customer sites. Hier Design is a Xilinx AllianceEDA partner.


HP announced the volume availability of its Intel Itanium 2-based workstations running Microsoft Windows XP 64-Bit Edition Version 2003. The company says developers can create Itanium 2-based technical and business applications, and therefore have a single desktop for both 32- and 64-bit applications.


InnoLogic Systems, Inc. announced that Artisan Components, Inc. has integrated InnoLogic's ESP-CV product into Artisan's verification process. ESP-CV provides functional verification coverage, verifying the equivalence of a SPICE-level implementation netlist against a behavioral-level simulation reference model.Artisan reports it is using ESP-CV to verify dual-port SRAMs, single- and two-port register files, and diffusion and via programmable ROMS.


Magma Design Automation Inc. has announced Blast Create, a front-end tool the company says will help logic designers synthesize, visualize, and evaluate the quality of their RTL code, design constraints, testability requirements and floorplan. Magma says the tool integrates logic and physical synthesis capabilities, full and incremental static timing analysis, design for test (DFT) analysis and synthesis, and power analysis. Blast Create does not rely on wireload models or physical design data, but does allow designers to build and analyze a flat, multi-million gate design. Therefore, it should be possible to identify and fix problems earlier in the flow.


Mentor Graphics Corp. announced that Faraday Technology Corp. has selected the Seamless tool as its co-verification environment for the DSP and microcontroller cores in its IP library. In conjunction with this announcement, Faraday will also offer its first Mentor Graphics Seamless Processor Support Package (PSP). The PSP will model the Faraday FD216 16-bit DSP core, which is the first in a series of PSPs intended for audio processing applications.


Also from Mentor Graphics - The company announced, "The ADVance MS (ADMS) mixed-language simulator was successfully employed in the development of the SiWorks SC-ALIU adaptive equalizer core. ADMS enabled accurate, fast simulations of the SC-ALIU's tightly coupled analog and digital blocks."


Vast Systems Technology Corp. announced that, based on performance comparisons of the newest versions of its Comet and Meteor embedded system development tools, cycle-accurate development of embedded systems using virtual platforms can be performed at real-time speeds, and developers can perform architectural analysis and cycle-accurate simulation of their embedded software up to 20x faster - raw processor simulation performance is now 5x faster. Presumably these figures refer to earlier versions of the tools. Comet and Meteor use a "virtual platform" as a surrogate for a "software-rich chip" that runs on an off-the-shelf PC to execute embedded software and predict its eventual
behavior.
Comet is used to construct and modify virtual platforms, and to analyze them when running a realistic software load. When the platform design is finalized, it is "frozen" for use in Meteor, which then is used to develop, edit, compile, and debug embedded software by running the software on the virtual platform.


Verisity Ltd. and YogiTech S.p.A announced that YogiTech has developed three new e Verification Components (eVCs) for the AT Attachment Packet Interface (ATAPI), Controller Area Network (CAN) and the Open Core Protocol (OCP). An eVC is a reusable plug-and-play verification component for standard protocols and interfaces, and is based on Verisity's e verification language and the Specman Elite testbench automation. The companies
say an eVC is a complete verification environment including test generation, assertion checking and monitoring, and functional coverage scenarios. They also say that eVCs are configurable and extensible to satisfy each specific verification environment's requirements. All three of the eVCs will comply with Verisity's e Reuse Methodology (eRM), which "codifies the best practices for eVC development, delivers a common eVC usage model and ensures that all eRM compliant eVCs will interoperate seamlessly regardless of origin."


ATAPI is an interface between a computer and its internal peripherals. It provides the command set for controlling devices connected via an IDE interface. CAN is a high-integrity serial data communications bus for real-time applications that operates at data rates up to 1Mbps. It is an international standard, ISO11898, used in automotive applications, industrial control, and factory automation. OCP an openly licensed, core-centric protocol that fulfills system-level integration requirements, and defines a bus-independent, configurable interface between IP cores and on-chip communication subsystems. ATAPI, CAN, and OCP are available through YogiTech, which is a member of Verisity's
Verification Alliance partner program.




Industry News - Devices


Agere Systems announced two integrated, single-chip Voice over Internet Protocol (VoIP) products. The company is offering both dual and single Ethernet-port versions of the SoC device, thereby permitting manufacturers to design IP phones to meet the needs of residential and enterprise applications. The two new IP telephony devices are extensions of Agere's complete IP Phone SoC portfolio.


Broadcom Corp. announced the BCM8022 10-Gigabit Ethernet to 10GBASE-CX4 retimer that enables 10-Gigabit Ethernet data transmissions over short distances for applications such as aggregating and stacking of network switches and routers. The BCM8022 was developed in accordance with the new IEEE 802.3ak (draft) standard, the 10GBASE-CX4, which is being developed to meet the demand for very low-cost 10-Gbps links that interconnect switches as customers move to 1000BASE-T attached desktops. The new single-chip Broadcom product supports 10-Gigabit Ethernet Attachment Unit Interfaces (XAUI) to 10GBASE-CX4, as well as standard XAUI to XAUI retiming for transport or backplane applications.


Cypress Semiconductor Corp. announced volume production of its field programmable zero-delay buffer (CY23FP12). The company says the CY23FP12 is a "high-performance, 200 MHz clock distribution device featuring a flexible architecture that can be customized to fit a wide range of applications. The single chip, which incorporates the functionality of an entire clock distribution portfolio, is implemented on Cypress's proprietary non-volatile silicon oxide nitride oxide silicon (SONOS) technology and is fully programmable via manufacturing facility or desktop programmers."


National Semiconductor announced a new family of low-noise, high-performance CMOS low dropout (LDO) regulators for low voltage, high current DSP, FPGA and ASIC applications.
The new LP385x family has output currents of 1.5 A or 3.0 A, logic-controlled ON/OFF, an error flag or a separate sense pin, over-temperature and over-current protection.


NEC Electronics America is reporting "first-time silicon success" in the design of a 1.6-million gate SoC and its first production use of Sequence Design's PhysicalStudio. NEC says the majority of the design ran at 160 MHz, including a timing-critical microprocessor block, while the rest of the design ran at 80 MHz. The SoC was built using "a mature 0.25-micron process technology," but the company says the design required NEC to stretch the design methodology to meet the required microprocessor performance. In NEC's words, "After achieving maximum results for processor speed using state-of-the-art physical synthesis, NEC Electronics America got additional added value using
PhysicalStudio for post-route optimization, which allowed the design team to achieve even higher processor speeds."


Royal Philips Electronics announced the 32-bit ARM7TDMI-S processor core microcontrollers using an 0.18-micron CMOS embedded Flash process. The 0.18-micron Flash process permits low 1.8V voltage operation, suited to real-time applications such as automotive, medical, networking, Internet connectivity, and battery-powered consumer products.


Texas Instruments Inc. (TI) introduced a fully integrated ADSL access router-on-a-chip, the AR7. The company says, "Through integration of digital and analog functions, as well as power management and hundreds of system components on one piece of silicon, TI enables up to 25% reduction in rest of bill of materials over competitive solutions." The AR7 combines a MIPS 32-bit RISC processor, a DSP-based digital transceiver, and an ADSL analog front end including line driver and receiver and power management.


Xilinx - In a major statement dated April 14th, the company announced a new family of programmable chips, the Spartan-3, that the company says will "propel programmable logic devices further into high-volume, low-cost applications traditionally served by custom chips with fixed architectures." Xilinx says it is "leveraging both 90-nanometer and 300mm advanced manufacturing technologies to achieve unprecedented density and price for FPGAs. By setting a new FPGA price-density standard, Xilinx will be able to target a $23 billion total available market and address new higher volume applications in the ASIC market."


Subsequent statements from multiple companies indicate that many vendors are taking the Xilinx claims seriously, and are interested in aligning their technology with the news.


Xilinx says it has two fabrication partners, IBM and UMC, and has achieved an 80% chip-size reduction compared to competitive products on 130-nanometer technology. In the same statement, Xilinx says, "Industry leaders are racing to advanced process and manufacturing technology.


Xilinx joins other leaders in their respective industries - industry giants such as IBM, Intel, and Texas Instruments - in spearheading adoption of 90-nanometer and 300mm manufacturing technologies to further separate themselves from the competition by taking advantage of the greatest cost reductions in recent semiconductor history."


Dan Hutcheson, President and CEO at VLSI Research Inc., is quoted in the Xilinx statement: "The companies that get into 90-nanometer production first will get a tremendous advantage in lower cost due to higher yields. The die shrink can also lead to much higher-performing devices. Rivals who are late in 90-nanometer process technology will fall behind and may not be able to catch up."


Richard Wawrzyniak, senior analyst for ASICs and SoCs at Semico Research Corp. is also quoted: "With today's announcement of low-cost FPGAs, Xilinx is positioned to initiate a new wave of innovative solutions aimed at empowering a whole range of applications that previously could not use FPGAs. The design alternatives open to engineers have been expanded by the new Spartan 3 family of FPGAs due to their high functionality, off-the-shelf availability and low cost structure; and clear advantages over custom ASICs when the major concern is to reduce costs and get to market faster."


Willem Roelandts, CEO and President of Xilinx, said, "With today's announcement, Xilinx has completely changed the economic playing field for FPGAs, opening up a vast new market opportunity. Now, designers can afford to choose FPGAs over traditional custom devices for a broader set of cost-sensitive, high volume applications - and get to market faster. As traditional ASIC and ASSP design starts continue to decline, we expect that FPGA design starts using Spartan-3 will ultimately fuel higher growth for PLD makers."


The new Spartan-3 family includes eight devices at prices starting below $3.50. First customer shipments of new Spartan XC3S50 (50K system gates for under $3.50) and XC3S1000 (1 million system gates for under $20) began last month. Additional family members will begin shipping in the summer 2003. Xilinx says the entire Spartan-3 family will be available in volume production in early 2004.


(Editor's Note: All of this news is well and good, but not everyone in the industry is buying into the excitement. There are serious, somber discussions going on in multiple quarters about the technical feasibility and economic justification for 90 nanometers, as well as heated arguments over the authenticity of the 'coming of age' of the FPGA market as competitor to the established ASIC market. Adding to the discord are various factions reigniting the Language Wars: Are FPGAs the darlings of the VHDL crowd, while ASICs a cause célëbre for the Verilog guys? The next several years will be nothing, if not interesting, for those who are watching these trends closely.)




Coming soon to a theater near you


NanoEngineering World Forum 2003 - Sponsored by IEC and running from June 23rd to 25th at the Royal Plaza Hotel & Trade Center in Marlborough, MA, this event is intended for a range of attendees: chief scientists and technologists, engineers, research directors, executives and strategic planners, educators, and venture-capital analysts. Organizers say, "Anyone whose business depends on the products and processes of applied engineering will benefit from this broad, but focused colloquy on the future of a technology that stands ready to change that future."


The conference is clearly going to "emphasize the necessary collaboration between industry and research interests," with various panels and tutorial discussions where participants will "take stock of nanotechnology's impact on industrial organizations with a unique parallel nanobusiness track for executives, examining the strategic business implications of nanotechnological advances for both established enterprises and start-up ventures."


One indication of the cutting-edge nature of the material being offered at the Forum is the percentage of presenters out of academia. Nonetheless, if there's money to be made in that growing bucket called "nanotechnology" as it emerges from universities and industrial R&D, this may be the place to learn where, why, and when. (
www.iec.org/events/2003/nanoengineering)


Wescon North America - If you're even remotely related to the semiconductor industry, you should be planning to attend IEEE-sponsored Wescon from August 12 to the 14th at the Moscone Convention Center in San Francisco, CA. That's because you'll be able to walk through the exhibit hall and take the pulse of the industry.


If things are hopping, you should go back home and start gearing up for the long-awaited upswing. If things aren't hopping, you should hunker down and prepare to weather yet another long winter of disappointing revenues and awkwardly worded quarterly statements. The same could probably be said of Semicon West - which will have come and gone in July - but Semicon is more about manufacturing, while Wescon, though smaller, throws a larger net across the semiconductor industry.


This year Wescon will be co-located with IEEE-Nano 2003 (which organizers say will focus on engineering issues related to nanoelectronics, circuits, architectures, sensor systems, integration, reliability and manufacturing in addition to fundamental issues such as modeling, growth/synthesis, and characterization) and the IEEE Photonics Packaging Symposium (which organizers say will provide an "open forum" for the presentation and discussion of topical issues and solutions
involving the packaging of passive and active photonic devices and modules). No matter which portion of the week's events you end up attending, Wescon organizers say, "If you're involved in hardware and software design, R&D test, manufacturing and board-level component technology, you need to be at Wescon North America!" You wouldn't be reading this newsletter if you didn't fall into one of these categories. Mark you calendars and go. (
www.wescon.com)




Newsmakers


Atrenta Inc. is adding distributors in Europe to sell and support Atrenta's suite of SpyGlass products. Atrenta already has a direct sales force in the U.K. and France to provide support and resources for its customer base in Europe. TRIAS Mikroelektronik GmbH will serve Germany, Austria and Switzerland, and First EDA Ltd. will serve the U.K. and Ireland.


Cyon Research Corp. and IBSystems, Inc. announced a cooperative agreement to support searching the databases of their websites, to promote sharing of CAD information across their respective audiences. Cyon's research engine, CADwire.net, will now provide an option to search databases of IBSystems' MCADCafe, GIScafe, PCBcafe, EDAtoolscafe, DCCcafe, and AECCafe. In turn, IBSystems web portals will provide an option to search the databases of CADwire.net. Under this agreement, each site has added a link to the other.


Forte Design Systems, Inc. announced it has raised $9 million in Series B financing. The company will use the new financing to introduce its family of high-level synthesis tools that automate systems design. The investment round was led by 3i US, and also included prior investors Infinity Capital and US Venture Partners, as well as a number of previous angel investors. The company announced that David Silverman, partner at 3i US, will join Forte's Board of Directors.


OEA International, Inc. announced VLSI One, Ltd. as their representative for Canada. VLSI One is a new company in Canada specializing in representing leading companies in the fields of EDA and IC technologies. Jerry Tallinger, Vice President of Marketing and Sales at OEA, said, "The Canadian EDA market is rapidly growing and ranks second to the USA as a top location for fabless chip companies, with over 250 companies engaged in ASIC and custom IC. Canada is a very important market, which is often ignored by many smaller EDA companies. Canada has a healthy economy with many high technology companies which could benefit greatly from the OEA technology."


Open Core Protocol International Partnership (OCP-IP) announced that Taiwan Semiconductor Manufacturing Company (TSMC) is joining the organization. OCP-IP says membership "will allow TSMC's customers to optimize design resources, shorten design cycles, and achieve greater first-run success, resulting in lower design costs
and faster time-to-market." OCP-IP members receive free training and support, free software tools, and free documentation.


Vast Systems Technology Corp. announced the closing of $6 million in Series C funding. The company says it will use the new funds to expand its sales and marketing efforts worldwide. Mohr Davidow Ventures (MDV) led this round of funding. Allen and Buckeridge, who led the Series A funding, also increased its investment in the company. MDV Principal Jim Smith will join Bill Goerke and Bob Christiansen on the Board, and Al Stein has been named Chairman of the Board.


In related news, Vast Systems announced the appointment of Paul McLellan as Vice President of Marketing and Business Development, and Dennis Heller as Vice President of Worldwide Sales. Both men will report directly to Graham Hellestrand, President and CEO. Previously, McLellan was Corporate Vice President of the Custom IC product line at Cadence. He joined Cadence when they acquired Ambit Design Systems. Prior to Ambit, McLellan spent 16 years at VLSI Technology and its Compass Design Automation subsidiary, where he was President of the subsidiary. He has 20+ years' experience in the EDA and semiconductor industries. Prior to Vast, Dennis Heller was with Avanti, where he was Vice
President of North American Sales. He joined Avanti as a salesperson in 1994, when the company was just beginning to ramp up sales. Prior to Avanti, Mr. Heller was at Sunrise Test Systems, Synopsys, and IKOS Systems. He has 15+ years experience in EDA sales.


Xilinx, Inc. announced that company co-founder Bernard Vonderschmitt, 79, will retire as Chairman of the Board as of August 7th, when the annual Xilinx shareholders meeting takes place. Company President and CEO Willem Roelandts, 58, will succeed Vonderschmitt as Chairman of the Board and retain his day-to-day responsibilities at Xilinx. Vonderschmitt co-founded Xilinx in 1984 and served as CEO until 1996, when Roelandts assumed the post. The company says, "Vonderschmitt was instrumental in guiding Xilinx from a Silicon Valley start-up to a billion-dollar-plus global enterprise." The company also announced that Jerry Fishman, President and CEO of Analog Devices, Inc., will
become Lead Independent Director. Fishman has been a member of the Xilinx board since 2000.




In the category of ...


Letters to the Editor


March 10th - Division of Labor (design versus verification)


Gaurav Agarwal - "I read 'To design is human, to verify is ...' Thanks for a very nice picture and industry-wide view of verification. Still, would it not be better to have chip manufacturers instead of EDA vendors as panel members? After all, chip manufacturers are the ones who decide whether verification engineers are needed or not."


April 14th - On deadline


Sean Morely, Senior Product Specialist for Synchronicity - "... and don't forget filing income taxes! Ah, the great balancing act. The journey really is the thing."


April 21st - From Margaret Mead to Caesar's Wife


Ian Getreu, DAC 2003 Chair - "Thank you very much for the very nice write-up on DAC. I have received comments from members of the Executive Committee that this was one of the warmest interviews they have seen on DAC. It is greatly appreciated. There was one typo that set up some humorous email-s. MPA [MP Associates] is employed by the Executive Committee to run DAC - they are not the employer. The e-mails were from a couple of members of the Executive Committee asking MPA for payments."


Nanette Collins, DAC 2003 Publicity Chair - "I can't thank you enough for the article on Ian Getreu and DAC. Even if I was not DAC's Publicity Chair, I would thoroughly enjoy it!"


Rita Glover, EDA Industry Analyst & Consultant at EDA Today, L.C. - "Regarding your EDA newsletter that came out this morning (which I always enjoy immensely), I was just wondering about the reference to 'Caesar's wife.' I used to think I was well read, but this is a new one to me and I'd like to understand it. Can you elucidate?"


(Editor's Note: A search on Google for "Caesar's Wife" produced many references, including: 1) "Caesar's wife is the guardian of Roman honor. She must be above reproach." 2) "Because I am Caesar's wife, my conduct has to be impeccable, to look right, to be beyond criticism." 3) "Caesar's wife wasn't permitted to even give the appearance of impropriety.")


April 28th - Critical Mass at U-M


John Sanguinetti, CTO at Forte Design Systems - "I enjoyed your column about the University of Michigan, my alma mater (BS, MS, PhD). They have indeed made great strides in the EECS department in recent years. You didn't mention the Dean of the Engineering College, Stephen Director, who I think has had a good deal to do with it. He is an EDA guy, being on the board of PDF Solutions and formerly associated with OrCad. Another top-notch faculty member is Karem Sakallah, who has done some really interesting work in logic design and synthesis."


Anon in Marketing - "Just got through reading this [article]. So this is about the trip you took with your son, right?"


(Editor's Note: Our daughter was looking at the PhD program in Computer Science (AI) at Michigan. She has since decided to attend MIT and will enter in the fall.)


April 28th - Closing comments and kudos from the University of Toronto


Kim Hailey - "In your [newsletter] today, there was one very little mistake. HSpice is currently a Synopsys product. Meta-Software merged with Avanti, which merged with Synopsys. Thanks for the great newsletter."


(Editor's Note: I would suspect that many people continue to think in terms of "Avanti tools," even as all of us know that Avanti is now part of Synopsys.)


April 28th - Industry News - Tools & IP


Tony Larson, Vice President of Marketing for Verplex Systems - "Thank you for your mention of Verplex's new Conformal DP in this week's EDA Weekly. I'd like to clarify a small, but important point about Verplex's new datapath verification product: Conformal DP is designed to verify the functionality of complex optimized datapath circuitry produced by datapath and synthesis tools. We don't verify timing, which is what the paragraph currently reports."


(Editor's Note: This is an important distinction. My apologies to Verplex. The April 28th issue of EDA Weekly has been corrected and is now available on-line.)


April 28th - Cooley twice over - Letter No. 1


Anon, ESNUG Reader - "[Here] is the challenge with NDA agreements. The same term and approach have come to cover a variety of business activities to the point that, if a customer or prospect isn't briefed 'under mutual NDA,' they feel cheated. (Why else, all of those high priced enclosed suites at DAC, for example?)


The thing that makes ESNUG such incredibly valuable reading to me is not that I can learn what vendors' plans are - though, if you don't like science fiction you shouldn't read business plans and vendor roadmaps - but that I get a very accurate picture of customer pain (even agony and, in some cases, near death experiences) that allows me to understand where the opportunities are and where the vendors will ultimately go.


Technically John asked 'See anything interesting under NDA? What did you think of it?' I suspect the answers he will get back are Vendor XYZ showed a compelling solution to speed up simulation by a factor of 10, or Vendor ABC showed us property checking that scaled to 6000 bits of state space.


The net impact will be for prospects to ask Vendor XYZ or ABC for their presentations, which is what the vendors want anyway - buzz.about something they have that's compelling, or at least interesting. There's something implicit in [John's] question that any good reporter or marketing person asks all the time at a conference: 'What have you seen that's interesting?'


Since most presentations are under NDA, it's implicit that what you saw may have been under NDA, and very likely anything that was interesting was under NDA. [John] could have left NDA off of this question and gotten the same answers. I believe that you should honor every NDA that you sign, but most expire pretty rapidly as the information comes into the 'public domain' of a small user community."


April 28th - Cooley twice over - Letter No. 2


John Sanguinetti, CTO at Forte Design Systems - "The answer to Cooley question No. 2 is Magma."


Tim Reeves, Matsushita Electronic Materials, Inc. - "The answer's right there when you click on the red page. It's some company called Magma."


Daniel Payne, Product Marketing Manager at Mentor Graphics - "This sounds like Magma, because there's a press release today saying: 'The end of synthesis as we know it is here,' said Venktesh Shukla, senior vice president of Marketing and Business Development for Magma Design Automation."


Anne O'Neill, Executive Director for the IEEE Solid-State Circuits Society "Letter No. 2 wasn't that hard. The URL of the sponsoring firm was in the image, if not linked. They are www.magma-da.com."


Gloria Nichols, Principal at Launch'M - " FYI, John posted later on his site that his readers told him that Magma was behind the ad."


Sean Murphy, MegaPath Networks - "If you go to the website, it's clearly Magma. It must have been updated since the question was posed. Take another look. That's the problem with living in Internet Time. The half-life of information accuracy is measured in hours."


John Cooley, ESNUG - "To answer your question in Letter No. 2, it was Magma just doing some pre-DAC marketing hype. When [Richard] Goering asked me about the Magma synthesis announcement, I laughed because it wasn't news. Magma had announced that they had synthesis when they first came to market 2 years ago. Nobody's ever written to me about using it in all this time, so I guess Magma's just trying to rustle up some interest in it this time around at DAC. I guess y'all got to have something to talk up at DAC, or the customers will walk on by. :)"


(Editor's Note: Perhaps the clever folks at Magma should write a White Paper entitled "Stealth and Cunning in Creating Buzz," or "Getting Editors to do Your Marketing Work for You.")


Week of April 28th - A query on the current status of SystemC


Cliff Cummings, Sunburst Design - "I think Gary Smith is right about Synopsys' Behavioral Compiler. ("Forte's Foray into EDA's Failure" by Alex Romanelli Electronic News, 4/29/2003) A great tool for certain applications, but way over sold. I was wondering if you have any opinion about SystemC suffering the same problem?


SystemC was oversold as the architecture-to-gates solution with free GNU C simulators. It didn't take long to realize that SystemC was terrible at gate-level simulation, and not too much longer to figure out that it does not compete well with Verilog and VHDL at RTL design and simulation. What does that leave? Architectural analysis and high-level testbench development. In the mean time, engineers, like myself, found good reasons to disbelieve anything positive that was reported about SystemC. I assure you, if we all saw three magnitudes of simulation-speed improvement, we all would have looked much harder at this new tool.


The next question is, since SystemVerilog is going to have a seamless C-interface, do we need SystemC at all? Will SystemC be the preferred interface to SystemVerilog or will designers just use plain old C? It is too early to answer that question, but I am seriously questioning what SystemC adds that I can't achieve with plain old C. Only time will tell.


The SystemC crowd touts the architectural capabilities of the language, but nobody will share what cool architectural things they are doing with SystemC. This leaves engineers like myself asking, 'Where's the beef?'


Maybe some of your readers could point us to some cool SystemC architectural models to convince us, the doubting types, that this really is a good thing. One lesson we are learning is, don't over sell your tools to a bunch of bright designers. They tend to be an unforgiving lot!"






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-- Peggy Aycinena, EDACafe.com Contributing Editor.


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