October 06, 2003
Toshiba's Richard Tobias
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When you're dealing with Richard Tobias, life is no joking matter. He's serious, intelligent, and focused - which is probably as it should be for the Vice President of the ASIC & Foundry Business Unit at Toshiba America Electronic Components, Inc. (TAEC). Tobias is also a walking encyclopedia of the technology and nuances around designing electronic devices and the CAD tools used to facilitate that process. And, he's a man with a mission - he's hoping to promote additional sophistication in the IP market and to persuade the EDA vendors, through whatever means necessary, to clean up their act and get their business models aligned at long last with their customers' business models. His
message is a serious one, well worth heeding.
Tobias' own career was launched amidst CAD tools. He started at Honeywell followed by Medtronic, both in Minneapolis, MN, then moved to California to work with AMD, and then Data General. With each of these stints, he was involved in the development of CAD tools. Yet over time, Tobias found himself evolving more and more into the design side of things, with particular emphasis on DSPs. That led him to the founding of WhiteEagle Systems Technology and a vigorous stretch of years heading up a team that successfully developed “lots” of SoC designs.
The WhiteEagle guys were obviously master craftsmen. They did both software and IC design, as well as board development for their product line. Everything that was easy or hard about a project, including the math algorithms for real-time computing, the WhiteEagle guys prevailed upon. Tobias says, “We didn't worry at WhiteEagle about how to implement a project - whether to implement in silicon or in software - we would just choose the best way to do it. We had a very versatile team and that was the reality for us.”
Eventually Tobias and his fellow WhiteEagle founders sold the company to QuickSilver Technology. Tobias was with WhiteEagle from 1992 to 2000, but after the sale to QuickSilver, lost interest in the effort and found greener pastures wherein to practice his craft and highly developed management skills.
He's now sitting in a VP's chair at TAEC, facing a tough economy, a stiff field of competitors and, by his own description, a less-than-satisfying set of CAD tool offerings from his friends in the EDA industry. He says, “It's not surprising that I know a lot about the CAD industry - I've designed tools and I've designed chips. More importantly, at WhiteEagle, we had a huge number of successful SoCs under our belts, some of the very first in the ASIC world. I really know this industry.”
Tobias on IP
Tobias says that companies like ARM, with their processor cores, were just starting to emerge as players in his early years with WhiteEagle: “At that time, a lot of processors were built as small pieces of silicon. That always presented quite an interesting challenge trying to incorporate them into a design. I was really happy when ARM came along. They helped us with our microcontrollers and [began to prove their worth as an IP provider].”
He adds, “Designing complex chips was an interesting challenge back then. It wasn't exactly obvious how to go about getting these things done - we were dealing with 10,000 to 100,000 gates on an SoC in the early 1990's (the equivalent of 1 million to 10 million gate designs today) - or how to get the tools to do the job. Developing the necessary tools could take over a year, which is why the attitudes towards [commercially available] CAD tools changed and the concept of IP began to change significantly, as well.”
Tobias is quick to point out that although things were challenging in the 'before time,' things aren't much better today: “I would say that the IP industry is still in its infancy. You still get commercial IP that doesn't work and until folks come up with a way to buy IP that's as robust a process as buying a chip and building a board - until folks get more assurance from the IP vendors that this stuff will work - it will never be a mature industry. It's never surprising that a piece of IP will work in the vendor's tests; however it's never obvious how it should work in my system, the customer's system.”
“Clearly today, we need standards. VSIA is trying, but it's such a hodge-podge, 'Do whatever you want.' There are de facto standards like AMBA, and smaller ones from IBM. Of course, Toshiba has its own internal standards that we're moving to make into external standards. Without standards, you simply can't connect all of this IP together.”
Referring to the history of PCB design, Tobias says, “If you look at a board and look at how the industry builds good boards, it wasn't so long ago that you had TTL parts and other NAND/NOR gates that you could buy, and there was a standard in voltage levels and how signals were handled [that helped put it all together on the board]. Basically, there were two kinds of bus structures - one defined by Intel and one by Motorola, to put it in simple terms. Then we had Multibus, VME and PCI, and all of these other kinds of protocols to connect boards together, or component sub-systems. The only way the board industry made all of this happen was to have standards. Twenty years
it was harder to build a board, but today with standards on power and behavior, it's possible to [design more successfully].”
“It's the same situation on a chip - without standards you can't connect the IP together. In a sense, using IP in a chip today is like the early stages [in board design]. Most IP today doesn't even consider if there's other IP on the bus and certainly I wouldn't say that ARM has been granted the de facto standard for the industry. Here at Toshiba, we've found a lot of deficiencies in the ARM standard. It's not the worst thing in the world, but there's still a lot to be improved upon.”
“In doing verification, the main flaw with every bus technology is that it doesn't consider how you can hook up 100 or 200 pieces of IP on the same bus. When you use any of the bus standards available today, you've got a mass of nets on top of a chip, which forces you to deal with the timing. I actually see this as a problem with every bus standard out there. Most busses can only hook up 10 pieces of IP, or less, before they start breaking.”
Tobias says that wiring ends up being a huge issue: “Basically, we keep saying that we have Moore's law, with our transistors getting smaller and smaller, but there's no Moore's law for capacitance on a wire. As we make our devices smaller, we don't have a corresponding Moore's law for wiring on a chip - the capacitance of the wire on the chip hasn't changed. It's true we are beginning to have different materials that can help, but we're still a long way from solving the problem.”
As a result of his obvious frustration with the current state of affairs in the IP industry, Tobias is pleased that TAEC is spending a lot of time working on the OCP-IP (Open Core Protocol International Partnership) standards project. He says, “One of the things we're doing here at TAEC is to put together a standard for the way IP should look when you purchase it - what kind of documentation, what kind of coding style, what kind of specifications need to be provided to the customer. Sonics put OCP-IP together, but we've always believed strongly in these types of interfaces. The issues around IP are not just about having a standard bus. A standard does allow you to test
pieces of IP
in a system in an orthogonal way, but the critical aspect of designing and verifying a system quickly is that you want to determine in advance of tape-out if the IP is going to work on that bus. The nice thing about the OCP-IP standards and the Sonics tools is that they create that kind of orthogonal testing environment.”
“One of the big issues with bus standards is that you have to spend a lot of time testing the arbiter. With an AMBA standard, for instance, you have to read/write to every register and be sure that it doesn't make a mistake. You have to design your device selector so that you don't write to two places at the same time. The other important thing about a bus is that you should be able to lay it out. We're getting to the point today where you've got anywhere from 5 to 100 pieces of IP on the bus. You don't want to have a big MUX on the bus that will make it difficult to lay out, as in the AMBA bus. These are some of the factors that are going into the OCP-IP standard - doing the layout
meeting the timing, and also being able to do verification.”
“Here at TAEC, we're also specifying to our IP vendors that they must give us C programs that allow us to run the IP on any processor, so that we can test the IP from the processor as well. It's absolutely silly to think of a piece of IP as not communicating with the processor. Every piece of IP on a bus is going to have to have something to talk to it. So you can see, we're not just talking about building a standard here, we don't want to just test the edges of the IP. We're talking here about testing IP that can function within a larger system.”
The forthright Tobias sees some hope: “I think TAEC is becoming a significant force in unifying all of this. We're providing a leadership role in trying to push the large IP vendors to write IP in a way that's right for us. Hopefully, we'll have some announcements soon in this area. We already announced the SoCMosaic custom chip program, in January 2003, which is a concept for designing chips that are IP-rich in a very fast way - for taking IP out of our library and generating the chip along with the software drivers and everything you would need for the SoC to be done - everything, in other
words, for developing chips quickly. We're pleased that several IP providers have been part of the initial SoCMosaic custom chip effort - Denali Software, GDA Technologies, Mentor Graphics and Sonics.”
For those wondering if the TAEC effort has led to any successes as yet, Tobias says, “We've just finished producing several chips out of this program. I think there isn't a single piece of IP on those chips that was developed in-house. That's a pretty interesting commentary on the success of this standards program - the chip is comprised totally of purchased IP and is currently running in the lab, exhibiting absolutely zero bugs in testing.”
Looking at the current situation in IP, Tobias suggests that an important part of the model for ASIC vendors in the future is to be a design integrator: “I think that this will be the new definition of an ASIC vendor. I'm so sure of that, in fact, I'm suggesting that guys who don't agree with me won't be in business in the long run. There are clearly several approaches to this, but I think that it's important to be good at design integration, no matter what strategy you use in accomplishing the feat.”
Tobias believes that designs with a hundred million gates are on the horizon: “There's lots of work ahead [to produce these chips], and it's going to be difficult with the current tools. But I like to think that if we can successfully integrate [lots of] IP onto a chip, then 100 million gates will be a no-brainer. If someone is going to have to design each gate, that's a lot of effort, but if you can leverage what other people have done, [these things are possible]. Clearly we need to have a good IP industry and the appropriate standards [to accomplish this].”
Tobias on EDA
Tobias says he has a “fairly large organization, one with a large headcount,” which means he speaks for a lot of tool users. Not surprisingly, he feels that he should have some sway with his EDA vendors.
“There's a sense of partnership between TAEC and our vendors, and therefore we're able to create a sense of urgency. Depending on the situation, we do everything you can think of to influence them to get the right EDA tools into our company. At times you have to threaten them - you can be threatening and still be a partner - which leads to a love-hate relationship. We know that the CAD tools are the only things that are keeping our business on the technical forefront, without them we'd die, but at the same time the tools aren't advancing quickly enough.”
Tobias says his concerns run deeper than just issues with the tools: “In every industry, the suppliers and the customers have to be as closely aligned as possible with their business models. The more closely you're aligned, the more money you can make and the better you can help the industry to progress. As we all know, EDA's been pretty stagnant for the last several years, it's not growing very fast at all. Unfortunately, the way people in EDA are making money today is by taking market share from each other rather than by growing their industry. It should be forcing them to look at the economics of the situation.”
“Consider Say's Law which says that if there's lots of supply in the world, supply is never an issue and you'll end up instead with a lot of demand. The law also says that if you align your customer's business model with your own, you'll participate in the wealth creation of your customer. An EDA tool today typically tracks a project on the design side up to the point of tape-out. Companies like Synopsys, Cadence, Magma have one main goal, which is to help people get their designs into production. That business model has meant that the EDA companies have been reasonably profitable historically, but there's something missing here.”
“I strongly believe that there needs to be an alignment between the business models of the EDA vendors and their customers - companies like Toshiba, IBM, the fabless start-ups, any of the companies that use EDA tools. How much time does it take to get a design into production and, once in production, what is the quality of the results? These are questions that should figure into an EDA vendor's revenue. It's an EDA vendor's job to help a product exist, while their business model should address the productivity of their clients. Any improvements in that area should be measured by the number of design starts - or 'tape-outs' as the EDA guys prefer to say. As an EDA vendor, you would get
money by getting things into production. The payment model should be based on that metric, one that's more in line with what the tools are doing.”
Tobias says the situation today is far from ideal: “The major EDA companies have a price for each particular tool, how much you have to pay to have access to a specified number of seats. But these numbers are very arbitrary - I might use one license or several licenses on a single chip. Basically, the EDA industry is far more interested in selling tools based on how many licenses I use, rather than on how efficiently I can get my designs into production, which is an absolutely bogus concept.”
Tobias is unequivocal: “EDA vendors should be thinking that if a customer has a chip that tapes out 3 weeks faster and, therefore, hits the market window faster, whether it take 50 copies of the license or just 1, it's the turn-around time on that design which should be important. If the vendors were to do this, [then and only then] would their business models be aligned with the business models of their customers. There would be more design starts and profits would increase for the customers and the vendors.”
“As it stands right now, we have times when we just don't have enough tools. We have to beg the vendors for licenses to give to our freelancers for a short period of time. But it always takes time to negotiate those arrangements. We never find ourselves saying in advance, 'Oh jeez, if I had more of this tool, I could get more work done,' because we don't know. Sometimes our teams stand idle for two days waiting for a license to be negotiated. If instead, everyone was motivated by turn-around time, again the basic economic theory says that more wealth would be created by the industry, and [ergo] there would be more wealth in the industry.”
Does Tobias try to explain his arguments to the vendors? “I tell [this stuff] to the EDA management all the time! But the problem is that they don't think that the financial analysts will understand the model. They've already convinced themselves that the current model works. But it doesn't!”
“I've also been talking with the financial analysts and have been getting some traction with them. My message to them is that, currently, the EDA model doesn't make sense because you only run a tool for a short time to get to tape-out. If you were to license a database, you would want to license it for a number of years, which makes sense because a database runs continuously for years and never stops running. Obviously for companies like Oracle, that means that they're motivated to keep the database running. But that's not how EDA tools are used. The EDA business model just doesn't match and it should be changed! Clearly, if the model were working, the industry would be growing
How about the royalty model? Tobias says that's not a valid concept with regards to EDA tools: “The royalty idea, taking a cut of the production revenue, is broken. The EDA vendor is not part of the chain of selling the silicon - they're not providing intrinsic value there. The reason that the royalty model works for star IP is because for a company like ARM, for instance, the company's IP is a selling feature for a product. But whether a chip has been developed using Cadence, or Magma, or Synopsys doesn't change the intrinsic value of the chip. The EDA tools have no way of affecting the sale of that chip - the vendors shouldn't be asked to have their revenue depend on whether the
or not. That would mean that they would have to [completely] understand the end market, [which they don't].”
Tobias says the situation is simple to understand: “Basically, an EDA vendor gets paid when certain events happen in the product's life cycle. If the vendors moved to a time-to-production-based payment model, they would have a motivating factor in a reduced turn-around time for the design. Designs come with some easily measured metrics of complexity - the number of gates, the frequency, the current technology, whatever. If I, the customer, can get the chip out faster, you, the EDA vendor, would make more money. And, in my model, the customer would pay for the tools, not for the FAEs needed to support the tools.”
Tobias says there would be an additional benefit from this model: “For most companies like Toshiba, EDA money comes out of a centralized budget usually paid by semi-corporate-wide money. The tools become a shared resource and every group [pitches in to] pay the costs. But if the customer had smaller CAD tool fees, there would be better accounting across business units. The costs of the CAD tools would be more fairly broken up. The business units would have more choices as well - they could pick what they really wanted to use. They could switch their flows around as they saw fit. It would allow me to give my various business units more choices, and [give all of us a] better way to
judge the success of each unit.”
He adds that this change would more closely reflect the situation as it stands today: “The reality is that all of the business units already have relationships with their CAD vendors, they already have support from the FAEs. Why not have them buy their tools based on those relationships?”
Tobias is on a mission and it sounds as if he intends to succeed: “I think that if companies like Toshiba push the EDA vendors, [they will respond]. Of course, there has to be a give and take between the customers and the vendors. If the vendors think something is truly bad for them, they won't do it. But their current business model is truly bad for the industry - something that can be easily shown.”
“We have 3, 4, and 5-year contracts with our EDA vendors, and it appears that their tools fall apart by the end of the time. Vendors should realize that if tools are no good by the end of an agreement, customers will definitely jump ship. Currently, the CAD companies aren't really motivated to be sure that their technology is best of class. And, with the current business model, they're enjoying a 3-year hiatus of not having to do anything about it. The CAD companies today are driven more by financial stuff than by creating correct technology for their customers. The truth is, for several companies that I'm aware of, if they keep going this way they're going to be in very sorry shape
in just a little while.”
“Of course, we haven't stopped internal tools development here at Toshiba. Our effort here in that area is incredibly huge, especially for certain classes of design where we have no choice but to use our internal tools. I'm telling you, though, that we don't do this by choice. We do it to provide a constant threat to the EDA vendors, to push them to improve their tools, and to correct their business models to be in line with our needs as the customer.”
“The wealth of our industry, across all of electronics, is dependent on creating new products in a timely fashion and as fast as possible, because we don't know which one will be the next killer app. What that means for us at Toshiba is that we have to be putting thousands of different products through our fabs each month, with the implication of having lots of products on the market at any one time. The EDA vendors need to be in line with that concept, have to be in line with producing as many products as possible, and providing the tools for that effort. The problem is today that the business models of the EDA vendors simply don't address that end goal. Something has to give
Industry News -- Tools and IP
Cadence Design Systems, Inc. has introduced Encounter Test Solutions, which the company describes as “the most comprehensive test solution available on the market to support a unified test methodology bridging design and manufacturing.” The new offering is aimed at the unique needs of product and process engineers who have experienced “large inefficiencies in time and effort when endeavoring to improve yield
by accelerating defect identification and linking design and manufacturing data.” Meanwhile, the company says the Encounter Test Solutions expands on IBM's in-house EDA “test tools and heritage,” acquired in September 2002.
Encounter Test Solutions is comprised of two products - Encounter Test Design Edition and Encounter Test Manufacturing Edition. Encounter Test Design Edition, which is intended for design and test engineers, includes automated DFT insertion, capacity for designs with more than 50 million gates, memory BIST, embedded core test, test compression with x-state masking, and high-coverage delay tests. Encounter Test Manufacturing Edition is a failure diagnostic environment that analyzes design intent and manufacturing information.
Also from Cadence - The company announced what it describes as “the industry's first integrated IC packaging design and signal integrity analysis solution: the Cadence Advanced Packaging Engineer 3D (APE-3D), a tight coupling of the industry-leading Cadence Advanced Package Engineer (APE) with Optimal Corp.'s 3D field solver engine.” APE-3D is “an electrical and physical design system that enables IC buffer designers and PCB system designers to explore, design, implement and verify interconnect topologies and electrical constraints through simulation. It also enables these users to create full or partial IC package simulation models to optimize system-wide
Jamie Metcalf, Vice President of Marketing for Cadence's PCB Systems Division, made these comments in a phone call discussing the new product: “The APE-3D release is a pretty significant announcement. Traditionally, people have used our APE (Advanced Packaging Engineer), and have used layout tools in combination with various third-party extraction and analysis tools. But as with all point tools, customers had to deal with integration issues and synchronization issues. Customers also had to deal with two or more companies to get support issues dealt with.”
“So what we've done here is to [acknowledge] that designers really need a 3D modeling capacity to adequately design packages. We did some benchmarking and research, and spoke with several customers, and found that the Optimal technology was very well respected in U.S., Europe, Japan, and Asia Pacific. Their tools have a very good reputation for accuracy and speed, so we got into a discussion with Optimal about working together. We're basically embedding their engine into our product. Up to now, we've been depending on point tools for 3D extraction, but now with this OEM relationship with Optimal, when you buy APE-3D, you get the engine with it. APE-3D is now a product for the
and physical design of an IC package that allows 3D characterization of solder bumps, wire bond, solder balls, and 3D modeling of complex grounds and power planes.”
Switching to other topics, Jamie Metcalf also told me during the same phone call, “The latest OrCAD release is interesting because, to be honest, there's been some tittle-tattle in the market place as to Cadence's level of commitment to the OrCAD business. I believe this OrCAD release has new functionality and demonstrates that we're still investing in the OrCAD line, and that Cadence is still promoting it. We have made some changes to our sales model for OrCAD where we've signed up with EMA to handle the sales distribution, and I'm happy to report that it's going great - those guys are 100% committed to promoting OrCAD. It's quite tough for a company like Cadence to mix business
the high-end market of ICs versus the high-volume market for OrCAD. But we're very pleased with what EMA has done and this release is a culmination of that [effort]. It demonstrates that we're still investing there and doing good stuff. We're still devoted to the product and don't want to listen to the naysayers out there. And we don't think our customers should either.”
Celoxica and Xilinx, Inc. announced that a custom edition of the Celoxica DK Design Suite will be included with the recently announced Xilinx ISE Embedded Development Kit v6.1 (EDK). The companies say that “the combination of Xilinx and Celoxica system-design software offers the most productive hardware/software (HW/SW) co-design environment and a direct route from C-based descriptions to high-performance platform FPGA implementation.”
CoCreate Software, Inc. announced that OneSpace.net is now available for orders and shipment. Companies may also try OneSpace.net software by registering for a free, seven-day trial. CoCreate says OneSpace.net is designed as a “lightweight, collaboration tool for engineering data and project teams.” It includes a secure project workspace, integrated meeting center for Web-based meetings, application sharing, instant messaging, decision and task tracking, and a 3D model explorer for evaluating product designs.
Fujitsu Ltd. and Synopsys, Inc. have announced a new design consulting service that the companies say will help SoC designers improve the quality of designs and reduce design cycles. The companies also say that the new service will combine “Synopsys' consulting expertise in logic and physical synthesis with Fujitsu's expertise in physical design technologies, and that the combination will provide integrated support for customers' design processes.” The service is now available in Japan and will be expanded to other markets in the near future.
Intellitech Corp. announced the availability of the Intellitech PT100 Parallel Tester. The company says the PT100 Parallel Tester is “designed to off-load in-circuit testers and in-line programmers and optimize throughput of digital test and configuration of PCBs incorporating the IEEE 1149.1 standard.” The tester is based on Intellitech's parallel test bus, which enables simultaneous test and configuration of an unlimited number of UUTs (Unit Under Test) over common industry busses such as IEEE 1149.1. While the UUTs are configured and tested simultaneously, individual access to each UUT is preserved. The tester uses a second technique to balance test times with UUT
to optimize the throughput and match the beat rate of a production line without complex line balancing and duplication of capital equipment.
Magma Design Automation Inc. and NEC Electronics America, Inc. announced the integration of the Magma's IC implementation system capabilities into NEC Electronics America's mainstream production flow. The companies say the capabilities have been validated with test designs, as well as production designs, ranging in size from 500K to 12 million gates. Wolfgang Roethig, Senior Design Engineering Manager at NEC Electronics America, is quoted: “We supplied the data in the Advanced Library Format (ALF) conforming to the IEEE 1603-2003 standard to ensure maximum correlation with our internal golden library. With this effort, we could qualify and deploy Magma's signal integrity
analysis, including extraction, delay, noise and electromigration analysis for production usage. With highly accurate analysis capabilities, engineers at our ASIC design centers can achieve a higher quality of results.
Mentor Graphics Corp. announced a flexible “development solution” that supports a variety of uses in the development, prototyping and verification of PCI Express-based systems in FPGAs. The company says the development solution supports endpoints, legacy endpoints, switches, advanced switches and root complexes, providing capability for rapid prototyping, development and debugging that is the main reason for the explosive growth in FPGA-based systems. The development solution can be configured with either Altera's Stratix GX EP1SGX25F or Stratix GX EP1SGX40G transceiver-based FPGAs. It also includes flexible PCI Express signal routing via Infiniband cabling, test
JTAG programming, passive cards and on-board DRAM memory.
Also from Mentor Graphics - The company announced the FormalPro Multi-Processor (MP) equivalence checking product. FormalPro MP has a scalable distributed architecture that utilizes multiple CPUs to increase the capacity and speed of verification and regression runs. The company says this product is the first of several new product developments for its portfolio of “scalable functional verification technologies,” and that FormalPro MP can accommodate “large, complex chips using a single workstation with multiple CPUs, or multiple networked workstations, to verify designs of 130 nanometers and below.”
Monterey Design Systems announced that Spike Technologies has completed three chips using the Monterey tool suite. The companies say that Spike Technologies was contracted to complete the designs for “one of the largest electronics companies in the world.” The largest of the three designs includes 18 clock domains and 500+ clock gating elements. Pradeep Vajram, COO of Spike Technologies, is quoted in the Press Release: “The Monterey tool suite allows us to accurately predict timing, power, and die size far in advance of the completion of the design. With this information, we can eliminate the
one thing that our customers most fear uncertainty.”
PDF Solutions, Inc. announced the pDfx design environment, with which the company says designers can optimize products for manufacturability before tape-out, and that the product is designed to be interoperable with the Cadence Encounter RTL Compiler; Magma's BlastFusion; and Synopsys' Galaxy Design Platform. The design environment will include modified IP library cell variants that will work in conjunction with the library currently used by designers for their target foundries and processes. The product is described as “one of the first available commercial products based on the OpenAccess database.”
Synopsys, Inc. announced its support for efforts to drive industry-wide adoption of the Advanced Switching (AS) Interconnect standard based on the PCI Express architecture. Synopsys is a participant in the Arapahoe Working Group (AWG) that announced, in September, the completion of the Advanced Switching specification and the formation of the Advanced Switching Interconnect Special Interest Group (ASI-SIG). Synopsys says it will participate in the ASI-SIG.
The formation of the ASI-SIG is described as “an important step to drive the Advanced Switching specification forward and to enable designers to develop scalable switched interconnect and data-fabric architectures based on the PCI Express standard.” Those involved express hope that the Advanced Switching specification will enable a standards-based building-block approach to wireless, communications, storage, telecommunications and embedded product development. The ASI-SIG expects the standard to be ratified by year's end.
Translogic has announced its HDL Companion product, an environment for developing and maintaining HDL designs. The Press Release says, “HDL Companion is designed for the text-based HDL designer. HDL Companion extracts complex design structures from HDL sources, which may consist of third party IP, legacy code and newly developed code, in just seconds. The resulting complete design decomposition offers information regarding numerous aspects of the design. This information helps in understanding unknown code and
maintaining complex HDL designs. The embedded VHDL and Verilog parsers also support incomplete design code and code that contains syntax errors.”
Chris van Veenendaal, President of Translogic, is quoted: “Many VHDL and Verilog power users are reluctant to adopt graphical HDL entry tools. HDL Companion perfectly serves them in their needs to quickly understand HDL code obtained as IP or inherited from colleagues, and guides them whilst developing new code. It also saves them from using expensive simulator licenses to perform these tasks.”
Coming soon to a theater near you
ACT 2003 - This is the second annual international meeting of the Axis Customer Technology users group, hosted by Axis Systems on November 5th at the DoubleTree Inn in San Jose. Organizers describe the meeting as an open forum where users of Axis products can exchange information, can hear about “real world” user experiences, and can see new trends in acceleration and emulation verification methodologies. The organizers say the sessions are technical in nature and focus on the best practices for complex chip design. This year's keynote will be given by Albert Yu, former Intel Senior Vice President, who has recently joined the Axis Systems' Advisory Board.
Yu's keynote is
entitled: “Time to Profit: Design and Verification Take Center Stage.” Hopefully he'll be able to tell us what we need to do to address that pesky bottom line. (
CoWare Inc. announced the management team for its Signal Processing Worksystem (SPW) business unit. Isaac Sundarajan will be Vice President and General Manager, Mark Creamer will be Vice President of Worldwide Sales, and Eshel Haritan will be Vice President of Engineering. The SPW business was transferred to CoWare earlier this month from Cadence as part of a system-level design (SLD) and verification-focused strategic alliance between the companies. Meanwhile, several of the executives at CoWare, including President and CEO Alan Naumann, are SPW “veterans.” Naumann was previously General Manager of the Alta Group, which managed SPW within Cadence.
Isaac Sundarajan joined CoWare in 1997. Prior to joining CoWare, he spent ten years at Cadence in multiple management roles. Previously Sundarajan worked at Intel as a CAD manager in the ASIC and Systems organization. Mark Creamer has 20+ years of experience in high tech, EDA and computer sales and marketing, including 8+ years at Cadence. Previously, he was a VP at Calico Commerce, and held various positions at iReady Corp., and spent 9 years at Hewlett Packard. Eshel Haritan joined CoWare as part of the recent alliance agreement with Cadence. He joined the Alta Group of Cadence in 1996, managed the SPW product line engineering, and since January 2000 has managed the Cadence System-Level
Design group engineering, including SPW, VCC, NC-SystemC and Test Builder. He joined Motorola Semiconductors Israel in 1985, where he spent 10+ years.
CriticalBlue announced the closing of its first round of private equity funding. The round was led by Pentech Ventures. The company also announced the promotion of co-founder David Stewart to CEO. Ben Hounsell, interim CEO and Co-Founder, will now serve as Vice President of Business Development for the company. He is quoted in the Press Release: “David Stewart's wealth of experience and contacts within the EDA industry and user community makes him the ideal choice to take CriticalBlue to the next phase of the company's growth. He is the ideal person to maximize our strong market opportunity and next stage. I'm pleased he's accepted this new role.”
The company also announced the appointment of Peter Denyer to its Board as a Non-Executive Director. Denyer was founder and CEO of VISION, which went public in 1995 and was sold to ST Microelectronics in 1999.
InTime Software Inc. and Giga Scale Integration Corp. (Giga Scale IC) have jointly announced the formation of Giga Scale IC, founded by J. George Janac, who will serve as Chairman, and Bill Sommer, who will serve as CTO for the new company. Giga Scale IC is privately funded and has been formed by way of a buyout of “certain key assets” of InTime. The founders say that the new company has “the mission to offer the first web-based Electronic Specification System for the semiconductor industry.” Giga Scale IC already has a product in the works - slated to be formally introduced on Monday, October 6 - which is aimed at reducing the risk and costs of doing
large IC projects. The two
companies will stay in close proximity, as Giga Scale IC's headquarters will be in Cupertino, CA, just down the road from InTime, which is also headquartered in Cupertino.
Robert Smith, President and CEO of InTime, is quoted in the Press Release: “Spinning out Giga Scale IC from InTime is a win for both companies. While both share a common vision and many similar goals, we each needed to focus our product lines to fully realize these goals.”
George Janac is quoted in the same Press Release: “Fundamentally, Giga Scale IC is working at the conceptual specification level of design, while InTime's software is directed at the register transfer implementation level of design. Our products will give engineers a reliable and easy-to-use means of doing design specification to early estimates of size, power, cost and yield. This addresses a different market need from InTime's RTL tools, though the tools are certainly complementary.”
Sequence Design announced that KeisukeYawata, President of The Future International, has joined the Board of Directors of its wholly owned Japanese subsidiary, Sequence Design KK, and will also become a member of Sequence's management advisory board. Yawata is an investment partner with Startup101 Ventures and Co-Founder of International AngelInvestors.org, Japan Chapter. Yawata has 35 years' experience in the industry and has headed several organizations, including Applied Materials Japan, LSI Logic KK, NEC, and NEC Electronics (USA). He also served as Vice Chairman of SIA Japan from 1989 to 1994. Yawata has a BSEE from Osaka University, and a Masters from Syracuse
University where he was a Fulbright Scholar.
In the category of ...
If you'd rather listen to Muddy Waters than Barbra Streisand, have decided to follow the A's rather than the apparently-we-don't-play-baseball-on-Wednesdays Giants, and are semi-comatose on the couch with flu and fever, you've only got one choice. Turn on tv and hope that you'll actually live to see tomorrow dawn.
Then if you can hang on for say, 5 or 6 hours, you'll get to see the A's start against the Red Sox, listen to a couple hours of the Blues, and still have time to see the A's finish against the Red Sox. At the end of which you'll know two things - you should own more Willie Dixon CDs and, if it's the bottom of the 12th with two outs and the bases loaded, don't play deep at third.
Letters to the Editor
September 29th - Make New Friends, but Keep The Old
Steve Wang, Co-founder of Axis Systems, Inc. - “Thank you for correcting your article, 'Make New Friends, but Keep The Old.' We are pleased that Gary Smith of Dataquest considers Axis' XoC to be the major breakthrough tool in ESL verification, enabling design teams, including software engineers, to quickly transition back and forth between simulation, acceleration and emulation modes for optimized performance and rapid debug of their entire system. XoC is an all-inclusive, unified system that reduces communication overhead and eliminates time-intensive integration efforts for design teams.”
(Editor's Note - Mea culpa to the Master, Gary Smith. I heard him say “Axys” when he'd actually said “Axis,” during the phone call that lead to the article on September 29th. The on-line version of the article has been corrected. Thanks to both Axis and Axys for their patience with my error.)
September 8th - Musing at MIT
Ed Caldwell, Senior PCB Librarian, Designer -
“EDA 2003 - Where do we go from here?”
“Over time, some things tend to change more than others do. In 1936, Austrian scientist Paul Eisler invented the printed circuit board (PCB). Of course, this didn't make the popular headlines. The demand for PCB's didn't really take off until 1943 when a need was established for a critical component used in anti-aircraft artillery, the proximity fuse. First manufactured in large quantities in the U.S., the proximity fuse was instrumental in bringing down the German V1 rockets.”
“Since the invention of the PCB, design and manufacturing methodologies have changed radically. Many people still in the business today will remember designing PCB's with pen and ink. However, design and manufacturing methodology has continued to evolve and change for the better, especially since the advent of the computer. In a very logical sequence, computers have helped design smaller, better, and faster computers. But although materials have evolved, fundamentally, the PCB has remained the same basic composition of laminated materials interconnecting conductors and insulators.”
“But how about those CAD/CAM tools, eh? CPU-based design and manufacturing tools have evolved in leaps, stumbles, and bounds. The design tools I use today are far more sophisticated than those [from] back in the 'good ole' days. To say that computers have revolutionized how we do things is a severe understatement. It is mind-boggling when I think about the leap from the drafting table to today's computer workstations.”
“Nowadays, the vendors creating and evolving these CAD/CAM application tools are competing heavily with each other, same as most every other technical business in America. And driven to out-do the competition, the application tool vendors, even when somewhat constrained by operating system rules, have as many different detail techniques for how to create a design as there are application tools times the number of people that use them. Any user that has changed companies, tools, and coworkers over the years will know what I am talking about.”
“Manufacturing and assembly process specifications can also be very different. The fine-tuning of fabrication and assembly processing by many vendors is an art in technique development, important as a goal to set a stronghold for market position and to streamline their particular production capabilities. The technical design service librarians working in companies that use several vendors as fabrication resources will understand the challenges here.”
“Typically, I have to build multiple versions of footprint geometry to be used at specific vendors for a single component in order to obtain the best pricing and throughput at each facility. In addition to the manufacturing and assembly house differences, there is also the fact that, in the worldwide market, there are often several different package specifications for a given part. I frequently encounter different mechanical specs for 'equivalent' components when multiple sources are involved.”
“It's not uncommon today for individual PCB design professionals to go out of their way to help each other resolve issues and share ideas as to how to do things, even across company divides. This unwritten solidarity is largely due to the diverse and complex spectrum of information and techniques that reside on the input (engineering and packaging), throughput (design and layout), and output (manufacturing and assembly) sides of the PCB business. And we are always looking for better ways to get the job done. (Which is one of the primary reasons technique can be so different.)”
“Speaking of better ways to do things
Where do we go from here? Wouldn't it be nice to be able to branch away from current packaging and assembly issues and variables altogether? I like to imagine being able to design a three-dimensional model of the entire electromechanical device (PCB) using techniques that construct all of the component attributes designated in the schematic with a methodology that is intimately connected between designing and manufacturing. You could call it the 3D Solid Circuit Design to Manufacture tool.”
“'What are you dreaming about?' you might ask
Well, board design tools today are basically two-dimensional. Although layer stacking and component height are factored into the design, the PCB design model is actually made up of two-dimensional layers. But what if you could design the board as a three-dimensional solid model? Instead of placing two-dimensional package outlines on a two-dimensional plane, the components would be constructed in three dimensions using materials and specifications in direct interaction with manufacturing technology.”
“In other words, supplement or eliminate the use of 'off-the-shelf' packaging by creating one module in a three-dimensional integrated framework that will generate one solid package for the entire 'PCB' design. Visualize taking the IC design process further by utilizing a 3D solid modeling tool to compose the fabrication and layering of substrates, materials, and connections with an integrated design-to-manufacturing process that yields an entire 'printed circuit block' in one component and you get the concept. Miniaturization is not a radically new idea. In fact, making PCB's and components smaller has been an ongoing quest since day one.”
“I like to think of today's conventional PCB structure as a kind of 'smart brick' that serves as the foundation for building a 'city of atoms' where the normally unseen electrons work. Actually, when I was a kid ripping my first transistor radio apart, that is what I thought. When I encountered the 'insides' of the PCB, I imagined that this must be some sort of tiny city populated with aliens that somehow make this 'radio' thing happen. (I was very young, but I am still not convinced my first impression was entirely wrong.)”
“Nevertheless, already technology is in place to fabricate embedded passive components within the PCB substrate and on the surfaces. Die stacking is becoming common practice to reduce the size of 'hot' consumer products such as cell phones. Three dimensional construction techniques are already yielding double the output from half conventional size transistor material.”
“I would like to be able to utilize a new set of tools that revolutionizes the process of circuit board design. What are the possibilities of performance and size reductions if we have the ability to create a PCB (package) in the smallest 'any' shape possible? The way I see it, the functions could be designed in the schematic the same as now, and the 'component' layout and construction could take place in the 3D Solid Circuit Design modeling tool. The 3D design tool could, in turn, drive the techniques of fabrication interactively with the manufacturing tools. Each component junction could be established within the 3D model precisely on the X,Y,Z where the junction function is most
efficient at the 3D CNC fabricator.”
“Imagine the performance increase possibilities without the lengthy interconnects between off-the-shelf components. The space savings would be revolutionary. Instead of picking and placing an SO-8 package, this process would pick and place material in conjunction with a chemical processing set of manufacturing tools that builds a super small sized integrated circuit 'block.' I can't imagine that many other designers haven't also wished for such tools that would take circuit board design to the next level. It would be a virtual block off the old chip.”
(Editor's Note: A new link was established in the September 15th issue of EDA Weekly intended to facilitate the receipt of Letters to the Editor. Unfortunately, that link was misdirected within the website to an incorrect e-mail address. That error has now been corrected.)
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-- Peggy Aycinena, EDACafe.com Contributing Editor.