[ Back ]   [ More News ]   [ Home ]
October 27, 2003
Dr. Richard Newton
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor


by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

For those of you who don't know, there is one over-arching prize awarded by the leadership of the EDA industry each year. The Phil Kaufman Award, founded in the early 1990's in memory the late CEO of Quickturn Systems, honors the accomplishments of individuals who are deemed to have made a "substantial, sustainable contribution to the success and advancement of the EDA industry that benefits the industry's tools users - electronic designers."


Past award winners include Hermann Gummell (1994), Donald Pederson (1995), Carver Mead (1996), Jim Solomon (1997), Ernest Kuh (1998), Hugo de Man (1999), Paul Huang (2000), Alberto Sangiovanni-Vincentelli (2001), and Ron Rorher (2002).


For the past 9 years, the award has been given at the annual EDA Consortium banquet in the fall, a semi-formal affair usually held in San Jose, where the glitterati of EDA come out in force to enjoy dinner and honor the Kaufman Award winner.


For the past 9 years as well, U.C. Berkeley's Dean of the College of Engineering Richard Newton has acted as MC for the event, graciously detailing the accomplishments and technology advancements attributed to each year's recipient. Newton is an articulate after-dinner speaker, one that always adds a measure of poise and bonhomie to the event.


Something is going to be very different at this year's EDAC banquet, however. Instead of Newton, Synopsys CEO Aart de Geus will be providing the after-dinner comments. An equally poised speaker, de Geus will undoubtedly also go to great lengths to detail the accomplishments and technology advancements associated with this year's Kaufman Award winner.


Why? Because this year Richard Newton, himself, has been named as the recipient of the award. Newton is widely admired in the industry and de Geus will have no problem soliciting a warm ovation from the EDAC dinner crowd when presenting Newton with his honor.


In light of the award, Dr. Newton was willing to sit for the following conversation, gamely answering dozens of random questions with candor and aplomb. Surely if nothing else, he deserves an award for having endured this particular interview. We spoke by phone.
[more]




Are the universities listening?


In light of Dr. Newton's comments, it was fortuitous to have been in attendance this week at a Roundtable Discussion hosted in San Jose by Cadence Design Systems. There was more to the daylong event than just the Roundtable, but I missed those other portions. Similarly, there was more to the Roundtable than just the following comments. However, these comments seemed a natural epilogue to the discussion above with Dr. Newton.


The Roundtable was moderated by Dr. Kurt Keutzer, also on the EECS faculty at U.C. Berkeley. At the end of the hour, during Q&A, a question was posed from the floor by a faculty member from the San Jose State University Electrical Engineering Department. He asked the industry panelist to detail what they skills they're looking for these days in their entry level employees - what should universities like San Jose State be teaching to answer industry's needs and better guarantee employment for their graduates?


Mike Liehr, Director of Foundry Enablement, IBM Microelectronics - “We need folks who understand and can relate to physical things - how to implement a design in transistors, how to design tools. [As importantly], we need people who can communicate well. Ours is a customer-driven business and we need our employees to be eloquent, to have superb customer-communication skills.”


Alan Naumann, President and CEO, CoWare, Inc. - “We're a fast-growing company - we added 80 employees in this past year alone. First of all, we want to know that a graduate has engineering co-op experience. Second of all, we're really looking for advanced degrees - a Masters Degree of more. We've got a team in Aachen, Germany, for instance, with seven PhD's and a Masters in the group. We need employees with a deep understanding of the issues, that hardware design is now hardware/software design. A new employee needs to understand computer languages, embedded processors, how a compiler works, and the algorithms for deep-submicon design. It's also [crucial] to know C++ or
some
object-oriented language. Finally, we need people who will go through walls to get things done. We've got teams right now in India, Belgium, Germany, and San Jose. If somebody intends to get something done, they've got to have the skills to work [in this complex environment] and be willing to push things to completion.”


John Bourgoin, CEO and President, MIPS Technologies - “We also need people who can understand algorithms and how to apply them to future projects. We're doing more and more projects these days [which require these kinds of skills]. It's important to understand programmable solutions.”


Chris Malachowsky, Co-Founder and Vice President of Hardware Engineering, nVidia - “We need employees who have a great understanding of the fundamentals, someone who can write a compiler. You can learn Java later - it's the fundamentals that are important at the beginning, not the applications. Most importantly, our employees need to have great problem solving skills. They need to know how to dissect a problem into its simplest parts. Our employees need to know how to learn and how to think.”




Industry News -- Tools and IP


Aldec, Inc. announced the Co-Simulation Wizard for Simulink, for use with the Simulink modeling and simulation software from The MathWorks. The company says the Co-Simulation Wizard gives system designers an “advanced co-simulation solution for verification of system models developed in Simulink and digital logic developed in Active-HDL. The co-simulation enables designers to achieve more efficient and bug-free code earlier in the design cycle. DSP functions are very efficient when implemented in FPGAs. Many system engineers are opting to actualize their algorithms in FPGA devices instead of traditional DSPs because FPGAs are often less expensive and are also ideal for
handling complex, redundant computation tasks often relegated to front-end processors.”


Altium Ltd. announced the release of a new TASKING embedded software development toolset that will target the R8C/Tiny microcontroller from Renesas Technology Corp., a semiconductor joint venture between Hitachi, Ltd. and Mitsubishi Electric Corp., announced last month. The TASKING R8C toolset has Altium's Viper compiler technology and integrated embedded development environment. David Noverraz, Product Manager of Support Tools at Renesas Technology Europe, “Altium's dedicated toolset provides the ability to develop highly efficient code which is both fast and compact, enabling Renesas Technology's customers to fully exploit this low-power and low-noise
microcontroller.”


Atrenta Inc. and Aptix announced they have partnered to develop a set of RTL coding rules for pre-silicon prototyping to facilitate mapping to Aptix's multi-FPGA prototyping platform. The rule-set is made available as the Aptix Policy for Atrenta's SpyGlass Predictive Analyzer. The companies say the rule-set is intended for both design and verification engineers and helps both groups follow best practices and ensure code compliance with design-for-prototyping principles.


For designers it provides a comprehensive set of rules around which to efficiently code their RTL for FPGAs. For verification engineers it ensures that they are receiving clean RTL while providing in-depth design information. More of the verification engineer's time can be spent discovering real design bugs as opposed to FPGA incompatibilities. The end result is a streamlined RTL-to-PSP flow, a more efficiently verified and validated SoC, and quicker time to market.


Cadence Design Systems, Inc. announced that Renesas Technology Corp. has standardized on Cadence SignalStorm NDC as the sign-off delay calculator for Renesas' 90-nanometer design flow. Hisaharu Miwa, Department Manager of EDA Technology Development Dept., Design Technology Div., LSI Product Technology Unit of Renesas Technology Corp, said, “We evaluated SignalStorm NDC using a 10 million-gate SoC design. SignalStorm NDC allowed us to complete timing signoff 3X faster than the current sign-off delay calculation tool at Renesas.”


Magma Design Automation Inc. announced that Teradiant Networks Inc. has taped out two multi-million-gate, 300 MHz, 0.13-micron hierarchical designs using Blast Fusion, Blast Noise and Blast Plan. The Teradiant chips were full-duplex, multi-service packet engine and traffic manager chips with 10 Gbps to 40 Gbps performance.


Pulsic Ltd. announced Version 4.0 of its Lyric Physical Design Framework. The new version extends existing routing technology in the tool to handle analog-specific requirements, including symmetrical routing (automatically routes nets/subnets in a symmetrical pattern), routing to pin current density widths (automatically route a net at varying widths to guarantee sufficient track widths at every point in the topology of the net to carry all pin current requirements), metal strapping (provides automatic via strapping between any signal metals on various layers), and angled slotting. In addition, the company says the internal RC extraction-driven constraints manager “guarantees
matching on a per-layer basis as well as the whole net or subnet.”


Synopsys, Inc. announced that the company's Professional Services has collaborated with Toshiba to develop the Reference Design Flow for Toshiba's Media Embedded Processor (MeP). Synopsys also says it will provide services to Toshiba's customers to install the flow. MeP is a soft (synthesizable) core with a configurable microprocessor architecture that can be customized for high performance multi-media applications. The Reference Design Flow is based on Synopsys tools, including Physical Compiler and PrimeTime. Toshiba provides synthesis scripts for the Reference Design Flow optimized for the MeP architecture. Synthesis scripts for the MeP Reference Design Flow will be
provided through Toshiba's web site.




Newsmakers


Virage Logic Corp. announced the appointment of Jim Ensell as Vice President of Marketing. Ensell will be responsible for worldwide marketing and will report to Adam Virage President and CEO Adam Kablanian. Previously, Ensell was Vice President and CIO at eSilicon. Prior to eSilicon, he held executive appointments at Zladn and Cadence Design Systems. Ensell serves as chairman of the IP Committee of the Fabless Semiconductor Association (FSA), where he leads an industry effort initiated by the FSA Board of Directors to address issues associated with the use of third-party IP in fabless semiconductor companies. He also led the formation of working groups addressing IP quality, education
and baseline business standards. Ensell has a BSEE from Villanova University and an MSEE from the University of Pennsylvania.


Cadence Design Systems, Inc. and Beijing Zhongguancun Software Education Investment Co Ltd, (a consortium of Beijing-based investment companies and the Beijing government) announced the opening of the $30 million Zhongguancun Cadence Institute of Software Technology (ZCIST). Cadence says that many technology vendors have contributed support for this initiative, including Sun Microsystems, which has already committed to sponsoring students.


Fan Bo Yuan, Vice Mayor of Beijing, will lead the inauguration ceremony with the unveiling of the plaque for the official opening. Meanwhile, Song Xiao Hai, Vice Chairman of ZCIST, is quoted in the Press Release: “[The] ceremony represents a remarkable combination of vision and determination. It shows how rapidly things can be achieved when organizations come together with a common goal. The institute is a landmark in China's development as a world-class IC and system design center."


Per the Press Release, The Institute is “designed with a vision to help transform China from an electronics manufacturing base into a world-class center for IC and system design. The 120,000-square-meter ZCIST is the first of its kind in the Asia Pacific region. Unlike other training institutes for IC design software tools, ZCIST will provide engineers with comprehensive IC and system design methodologies, skills and knowledge to significantly increase their design capabilities.”


Ray Bingham, Cadence President and CEO and Chairman of ZCIST, is quoted in the Press Release: “Electronics manufacturing is continuing to shift to China, and all the indicators are that China's semiconductor industry will continue to grow faster than in the rest of the world. Cadence and the Beijing government share the same vision - to nurture IC design talent in China with a view to strategically advancing China's electronics industry. With the exceptional level and quality of training that ZCIST will provide, we believe that local post-graduate engineers will become world-class design engineers, and China a hub of world-class IC design in the future."


Also per the Press Release: “ZCIST is located in the Beijing Zhongguancun Science Park, an area dedicated to R&D and other activities in a variety of disciplines, including integrated circuits, biotech and software. It has been designed to provide training for up to 1,000 residential students per year with courses ranging from three to 12 months. The institute will offer six bilingual courses covering practical and advanced training on system level design, logic design and verification, synthesis and place and route, analog/mixed-signal design, custom IC layout design and high-speed PCB design.”




In the category of ...


An e-mail exchange


Hi Ed,


I read your interesting letter, “EDA 2003 - Where do we go from here?” and had a few questions/comments. Would welcome your feedback if you have the time. I work for Cadence, in the PCB group responsible for our strategic marketing.


It seems to me that you are proposing a technology that looks very much like System-in-Package (SiP) whereby bare die and passives can be connected together and stacked on or in a substrate. Even so, SiP is still probably best designed in 2D, while 3D can be used when needed (for example, when looking at form factor issues). Many of the original PCB CAD systems were built on top of MCAD systems and some had very good 3D capabilities - the industry moved away from this approach for a reason. The reason I believe was to optimize for PCB design - a 2D approach was more productive.


I'd also like to point out that although packaged components have their problems, they also provide a major benefit - the ability to integrate IP from multiple sources at low cost and by anyone (who has the inclination). Could the same be said for SiP? No. SiP will only be used in high volume or very expensive low volume (e.g. the military, supercomputers).


Regards,


Jamie Metcalf

Vice President of Marketing

Cadence's PCB Systems Division



Hi Jamie,


Thank you. I am very glad you found my letter interesting. You have made excellent points in your comments.


I agree that current PCB Design is sufficiently productive in the 2D format. The 2D environment gets the job done and accommodates a wide range of resource talent. Three-dimensional design, on the other hand, is more challenging and would narrow the range of design resources.


Packaged components will not be replaced any time soon. Likely never. And, as you say, the ability to integrate IP from multiple sources helps businesses to compete, which is a matter of survival.


My concept is probably more palatable outside the business world. For example, a significant part of my inspiration is the article/interview from Peggy Aycinena at EDA Weekly, “Musings at MIT,” wherein she quotes MIT Computer Science Professor, Srinivas Devadas:


"In academics, you define a problem and work on challenges that are not necessarily important to industry. Once a problem is established, industry will take over. In academia, however, it's nice to enjoy the problem for a while [before that happens]."


What I am proposing would initially be far more expensive compared to conventional methodology in design and packaging. In order for costs to become competitively palatable, the process methodology would need to develop into some mature state. This is not a proposal to compete in the marketplace today, but it is a proposal to compete with what we are capable of doing.


In my image modeling, I am seeing circuit blocks (boards) built interactively between design and fabrication. I am seeing a computer workstation with 3D modeling application software (similar to ProE or SolidWorks, etc.) that is interacting real-time, as the process dictates, with a fabrication station.


I am seeing the fabrication station as an evolved set of CNC machines (or machine) that is capable of processing raw materials under guidance and control from the design to manufacturing station engineering team. This is perhaps the most aggressive aspect of my imagining. The raw material processing capability at the fab station would need to encompass the entire spectrum of attributes necessary to construct any of the electronic component characteristics that establishes a functional performance - from substrate layering to passives to actives to connectivity to hermetic sealing. The manufacturing fabrication station would be the greatest challenge of the system.


I believe my dream machine already exists in slices today. It just needs some folks with the right skill sets to piece the puzzle together. I would expect that once the system is matured, there could be more of a market migration from pre packaging to process packages. Meaning, the “Block-off-the-old-chip” design-to-manufacture system would become more of a “package” that is marketed and distributed instead of the SO-8's, 0402's and so forth.


I think that if we don't pursue this, we are missing an opportunity to evolve into a next generation of performance and packaging in electronics.


Regards,


Ed Caldwell

PCB Designer & Librarian




On a personal note
Thanks to so many of you who wrote such poignant and personal letters in response to my story last week of cancer in my family. It was especially moving to hear that some of you were prompted to make appointments for your annual exams.








You can find the full EDACafe event calendar here.


To read more news, click here.



-- Peggy Aycinena, EDACafe.com Contributing Editor.