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March 01, 2004
Predicting EDA's future growth -- and, is Moore's Law dead, or has the paradigm shifted?
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor


by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Publisher's Note: There's a New Editor Coming to EDAWeekly Soon!


Beginning next week Dr. Jack Horgan takes over the reins as Managing Editor of EDAWeekly. Jack is best known to you for his exemplary work on our Quarterly EDA financial report. You can read a sample in this issue. Dr. Horgan is a CAD expert with years of academic and industry experience and we are honored to have him onboard. I'm sure you'll enjoy the depth of coverage and industry insight he brings. Welcome Dr. Jack!




Predicting EDA's future growth -- and, is Moore's Law dead, or has the paradigm shifted?

By David Heller


In this week's EDAWeekly we'll take a detailed look back at the performance of the EDA industry over the past quarter, and also look into our crystal ball to see if we can divine the future.


Before we look at the past, let's put the cart before the horse, put on our swami's hat and peer into the future. The crystal ball was a bit clouded at yesterday's EDA Consortium CEO Forecast and Industry Vision panel meeting, held at Virage Logic's facility in Fremont, California.


The meeting was moderated by Bill Freichs, an industry analyst from the D.A. Davidson Company who admonished the six distinguished CEOs and panelist to, “Be sure you forecast a forecast!” After a chuckle, Cadence's CEO Ray Bingham took the floor to say that, "After coming out of a two to three year downturn this is now a defining time. The economy has begun recovering, the stock market is up -- but we have huge technological problems to be solved. The challenge is to continue the Moore's Law dictum of smaller and faster, but now we've got to facilitate making chips more affordable - cheaper. This problem and challenge offer the EDA industry a definite opportunity." Ray said
that revenue for
logic IC's is growing from $50B in 2001 to a projected $86B in 2006. He also said that the FPGA market, although small, is growing at an extremely fast rate. He pointed out that the growth rate for ASICs is slowing and that the ASSP market (Signal Processing) is huge but is also showing little growth. SoC is “the sweet spot for real growth,” and Ray predicts a 7% to 10% growth in the EDA industry this year based on growing silicon R&D expenditures, a high renewable license base, and an improving economy.


Adam Kablanian, CEO of Virage Logic took the podium next and proclaimed loudly, “Moore's Law is broken!” Adam's contention was that Moore's Law is not a law of physics but an economic law based on supply and demand. He said that the cost of designing one project at 90 nanometers, for example, costs in excess of $30 Million, and that there are very few applications, especially consumer based-applications that can justify this cost. He said that the majority of designs will continue to be done in past-generation technologies, which are “just fine for the majority of applications.” Adam said that the EDA industry's challenge is to reduce design time by reducing the
number of engineering hours it
takes to produce a design. His solution, which he believes rightly since he's president of a major SIP company, is SIP. He said that more will be spent on SIP moving forward than on EDA tools. Adam was optimistic about the future saying that the SoC market is up, a major recovery is on the way, and the semiconductor industry is healthy. So, 'up' was Adam's projection.


Next up was Aart de Geus of Synopsys who began by saying that a team of high-level market analysts put together his marketing projection, and that they even guaranteed it! “They said that if the projection didn't come to fruition, they'd write another one for free.” Aart agrees with the other panelists that cost has been added to the Moore's Law equation, but stated firmly that, “Moore's Law will happen, and on time!” Aart also believes that there's a lot of growth potential in the SIP marketplace --- backed up by the recent announcement that Synopsys is to acquire
Monolithic System Technolgy and Accelerant Networks, designed to expand their IP portfolio. Aart also said that there's lots of interest in DFM
(Design for Manufacturing), yet another way to achieve lower costs. You'll have to forgive this reporter. I didn't scribble down Aart's projection, but I know it was up beat!


Entrepreneur Kathryn Kranen, CEO of start-up Jasper Design Automation said that design verification takes up as much as 70% of the design cycle, and reducing this time would greatly lower the cost of the final product. She said that the consumer market is hot, and that price is king. Reducing the cost of goods to the end-user is the main challenge. Kathryn also put in her vote for “Moore's Law is broken,” and emphasized that cost is part of the equation now. As far as predicting the future, well, Kathryn deferred to “Gary Smith's numbers.” Gary is EDA analyst for Gartner, Inc. I haven't seen this report, so I can't comment. If you've looked at it please drop
me a line and we'll publish
the numbers in our next EDAWeekly issue.


A jovial Wally Rhines, CEO of Mentor Graphics was up next stating that the semiconductor industry is in a long and sustained recovery, and that the EDA industry traditionally lags. He then went on to tell us of his quest for that magic 'leading indicator,' the one Holy Grail that accurately predicts the timing of EDA's future growth. He dismissed semiconductor R&D as not correlating with EDA, and also dismissed capital equipment expenditures as being too volatile. Wally said that EDA is based on design starts, not industry revenue, and thinks he's found the indicator in the haystack: Photomasks! He presented a chart that shifts the photomask industry's revenues four Quarters to the
right, and viola! -- an almost perfect correlation to EDA revenues. If the photomask model works Wally predicts a very “robust recovery” beginning in the third quarter of this year. If not, well, 5% looks good to him.


Last up to bat was Rajeev Madhavan, CEO of Magma. Rajeev pulled out two cell phones, both with different high-tech features, and said that the goal is to combine all the bells and whistles into one small device. And to do this he said, "We're going to need to push to smaller geometries, like 90 nanometer design. Our goal is to make our customers more profitable," he continued, “and to do this we've just got to make Moore's Law economically feasible. We've got to reduce the cost of silicon.” Rajeev's forecast for EDA industry growth this year is "in the 7% range," and he feels it will track along with semiconductor industry performance.
Gartner 2004 Semiconductor Forecast


So, what's the Moore's Law consensus? It's not dead, but the paradigm has shifted to include a third component, cost. And, what's the real forecast for this year? According to the panelists it's in the 5% to 8% range. But, I for one am going to be keeping a very sharp eye on the photomask industry!


The entire panel discussion, including some very interesting Q&A, was filmed and will be available on the EDA Consortium web site (
www.edac.org) in a week or so. We'll point you over there when it's up so you can see this event for yourself.




Commentary:


EDA Industry Update February 2004 --

What did the Last Quarter/Year Bring?

By Dr. Russ Henke and Dr. Jack Horgan


In
December 2003 EDA Commentaries by the authors (published on EDACafé.com), the then-current yearly and quarterly financial performances of a selected group of publicly traded Electronic Design Automation (EDA) companies were analyzed and compared. Expectations regarding the future financial performances of these same EDA entities were documented as well. This February 2004 report covers their performances for the fourth quarter of 2003 as well as for the full year 2003.


Preface


Based on news reports in the common media, it would appear that the general US economy has been improving in recent quarters. The US Gross Domestic Product had a spectacular third quarter with 8.2% growth and a lower but still positive fourth quarter with 4% growth. On Wall Street, the Dow Jones, S&P and Nasdaq rose 24%, 26% and 50% respectively for the 2003 year. Productivity increased 4.2 percent in the nonfarm business sector during 2003. Mergers & Acquisitions are on the rise as 2004 begins.


What about the electronics sector? During a February 2, 2004 webcast on "Fourth Quarter Results and Short Term Outlook,” Doug Andrey, Principal Analyst for the Semiconductor Industry Association, presented data for the semiconductor industry as shown in Table 1 below:


Product Line ($B) 3Q03 4Q03 4Q vs 3Q 2002 2003 2003 vs 2002
Discrete 1.42 1.56 9.9% 12.3 13.3 8.1%
Optoelectronics 2.54 2.83 11.4% 6.8 9.5 39.7%
Analog 6.81 7.52 10.4% 23.9 26.8 12.1%
MOS Microprocessor 7.34 7.92 7.9% 23.9 27.4 14.6%
MOS Microcontrollers 2.57 2.66 3.5% 9.4 10 6.4%
MOS DSP 1.58 1.76 11.4% 4.9 6.8 38.8%
MOS Logic 9.58 10.5 9.6% 31.3 36.9 17.9%
MOS Dram 4.62 5.11 10.6% 15.3 16.7 9.2%
Flash EEPROM 3.07 3.97 29.3% 7.9 11.7 48.1%
Other 5.3 6.9 30.2%
Total 39.53 43.83 10.9% 141 166 17.7%

Table 1 Semiconductor Industry Report - SIA


The total semiconductor worldwide market reported $166.4 billion in revenue versus $141 billion in 2002, a growth of 18%.
More ...





Cadence Enhances its Virtuoso Platform with New Chip Integration for Fast, High-Performance Custom Design


Virtuoso® custom design platform

CLICK IMAGE TO ENLARGE
Cadence announced today that it has optimized its Virtuoso® custom design platform with the availability of a new chip integration flow, coupled with the newest release of its Virtuoso Chip Editor. They state that by using these solutions together, designers will, for the first time, be able to perform full-scale physical integration across multiple design domains, including analog, custom digital, RF, memories/arrays, and digital standard cells from a full custom point of view.


"The chip integration flow, (as shown in the accompanying flow chart), is a key component of the Virtuoso platform and it is the first of its kind in the industry enabling semiconductor manufacturers to bring multiple design domains together into a single chip implementation," said Felicia James, vice president and general manager of the Cadence Virtuoso custom IC design platform. "With this advanced custom design flow, customers can resolve the challenges in designing mixed-signal ICs so that first-pass silicon can be achieved much faster and with greater predictability.”
Read the complete story here.




Weekly Industry News Highlights


NVIDIA Selects Magma's SiliconSmart Characterization and Modeling; Characterization Critical in High-Performance and Low-Power Nanometer Design


Accelerated Technology Builds on Its Success in the Cellular Phone Market by Becoming a Member of the Renesas Technology's SH-Mobile Consortium


Synopsys' Proteus Optical Proximity Correction Software Delivers Near Linear Performance Increase Using 1000 Intel(R) Xeon(TM) Processors


Elliptic Semiconductor Licenses its IPSec Core to Centillium Communications


Gartner Forecasts Worldwide Semiconductor Revenue to Increase 23 Percent in 2004


Synopsys to Acquire Monolithic System Technology and Accelerant Networks


More News ...




Upcoming Events...


DVCon 2004

Date: March 1 - 3, 2004

Place: DoubleTree Hotel

San Jose, CA USA Nothing stimulates the innovative juices of the engineering community within our industry as the two most overriding emotions - fear and frustration. The fear part comes when it is clear that large SOCs are a necessary consequence of the appetite for ever increasing complex systems using ever decreasing semiconductor geometries. With the cost of semiconductor tooling hitting the roof, system development times reducing, larger IP blocks of suspect origin (from a verification point of view) are being incorporated, and the sheer complexity involved- there is much to fear. The frustration comes into play when current EDA tools driven from higher level language descriptions are
applied to help mitigate the fear, and while they do their best, they don't quite have that calming effect that one is seeking when chip-zilla goes to tape-out.


nVisage/Protel DXP Schematic - Introductory

Date: March 9, 2004

Place: EDA Solutions Ltd, 2nd Floor Eleanor House

33-35 Eleanor Cross Road, Waltham Cross, Herts,, EN8 7LF

United Kingdom

Starts: 09:30

Finish: 16:30 (Approx.)

Description of course: A one-day course designed to introduce the features and functionality of the nVisage (or Protel DXP schematic) system. Ideal for delegates just starting with this powerful schematic software or for those requiring a more formal introduction to the concepts and operation of the system.

Contact: Sales Department

Tel: +44 (0)1992 762005

Fax: +44 (0)1992 762006

Web:
http://www.eda.co.uk

Email:
training@eda.co.uk

Price: $495.00


Design and Verify Complex Mixed Signal Systems on a Chip

Date: March 10, 2004

Place: San Jose, CA USA

Mentor Graphics cordially invites you to attend a FREE "Hands-on" Technical Workshop to use the complete front to back Analog, Mixed Signal design Flow using the IC Suite of tools in conjunction with a foundry supplied design kit.


Calibre in Your Design Framework

Date: March 10, 2004

Place: Atlanta, GA USA

Mentor Graphics invites you to attend this FREE technical seminar focused on the integration of the Calibre tool suite into the Cadence Design Environment.


Join us at this half day technical seminar to get a strong understanding of how Calibre is tightly integrated into many of today?s most popular design environments to provide fast execution of Calibre, LVS, and xRC and provides designers access to a single flow for physical verification and parasitic extraction.


Protel DXP Training Courses

Date: March 10 - 11, 2004

Place: Staffordshire University

College Road, Stoke-on-Trent, ST4 2DE

United Kingdom

Starts: 09:30

Finish: 16:30 (Approx.)

Description of course: A two-day course designed to introduce the features and functionality of the Protel DXP PCB layout system. Ideal for new users or those requiring a more formal introduction to the concepts and operation of the system.

Contact: Sales Department

Tel: +44 (0)1992 762005

Fax: +44 (0)1992 762006

Web:
http://www.eda.co.uk

Email:
training@eda.co.uk

Price: $995.00


Full and Semi Custom layout technique for designing a Chip

Date: March 11, 2004

Place: San Jose, CA USA

Mentor Graphics cordially invites you to attend a FREE "Hands-on" Technical Workshop to experience the power of Mentor Graphics Physical Design creation tools. This is an in-depth part of a workshop series highlighting the complete front to back Mentor Graphics Analog, Mixed Signal design Flow.


PCB Design Conference West

Date: March 15 - 19, 2004

Place: San Jose Convention Center

San Jose, CA USA PCB Design Conference West is the premier West Coast conference and exhibition for PCB and HDI engineering, design and manufacture professionals. The 13th annual PCB West will return to the San Jose Convention Center, a venue that is situated in the heart of Silicon Valley and provides attendees with a variety of restaurants and attractions within an easy walking distance. The five-day conference will offer an outstanding selection of technical PCB- and HDI-oriented courses, including full-day Professional Development courses and a Technical Conference (March 16-18) of short courses. PCB West also features a terrific two-day product and service exhibition (March 16-17) and
a variety of free events for conference and exhibition-only attendees.


SEMICON China 2004

Date: March 17 - 19, 2004

Place: Shanghai New International Expo Centre (SNIEC)

Shanghai, China As the semiconductor industry continues to advance and expand in China, SEMICON China 2004 will be the venue for semiconductor, equipment, materials and services companies to enhance their business opportunities in China.


ISQED04

Date: March 22 - 24, 2004

Place: DoubleTree Hotel

San Jose, CA USA The 5th International Symposium on Quality Electronic Design, ISQED 2004 is a premier Design and Design Automation conference, held in technical sponsorship of IEEE EDS, IEEE CPMT, and in cooperation with IEEE CASS, ACM/sigDA, and Fabless Semiconductor Association (FSA). ISQED is the pioneer and leading conference dealing with design for manufacturability and quality issues. Conference proceedings are published by IEEE Computer Society. Proceedings CD ROMs are published by ACM. The ISQED'04 conference spans three days, Monday through Wednesday, in three parallel tracks, hosting near 100 technical presentations, six keynote speakers, three panel discussions, workshops
/tutorials and other informal meetings.

Contact: Dr. Ali Iranmanesh
Email Contact


Calibre in Your Design Framework

Date: March 24, 2004

Place: Baltimore, MD USA

Mentor Graphics invites you to attend this FREE technical seminar focused on the integration of the Calibre tool suite into the Cadence Design Environment.


Join us at this half day technical seminar to get a strong understanding of how Calibre is tightly integrated into many of today?s most popular design environments to provide fast execution of Calibre, LVS, and xRC and provides designers access to a single flow for physical verification and parasitic extraction.


electronicaUSA Embedded Systems Conference

Date: March 29 - April 1, 2004

Place: Moscone Convention Center

San Francisco, CA USA Expecting more than 500 exhibitors and 18,000 attendees for its debuting show in 2004, electronicaUSA with the Embedded Systems Conference will be the largest annual North American event exclusively focused on electronics systems design. electronicaUSA with the Embedded Systems Conference is an annual event for the international electronics industry where the latest technologies are introduced and business gets done. It features a series of technology conferences and business sessions offering insights and practical solutions, and an exhibition showcasing cutting-edge hardware, software, tools, and the full spectrum of system components. Attendees and exhibitors alike
can learn relevant new skills, meet and talk with vendors, network with peers, and develop new strategic partnerships-all under one roof, at one time.


More Events...




--Contributing Editors can be reached by


You can find the full EDACafe event calendar here.


To read more news, click here.



-- Peggy Aycinena, EDACafe.com Contributing Editor.