August 29, 2005
Power Integrity with Sigrity, Inc.
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| by Jack Horgan - Contributing Editor
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Last week I wrote about low power featuring Golden Gate. This week the editorial is about another aspect of power, namely power integrity. I interviewed
Jiayuan Fang, founder and president of Sigrity Inc., along with Teo Yatman, the VP of Business Development and International Sales, during DAC. The company has recently introduced CoDesign Studio which combines its Speed2000 electrical simulation tool used for package and PCB design and XcitePI, a dynamic-noise simulation tool used for IC power grids, to do cosimulation of package, board and IC.
What is you background?
I received my Ph.D. from UC Berkley. I started my career first as a university professor. My first job was at the State University of NY, SUNY at Binghamton. In the 1990s I moved to Santa Cruz and was a professor of electrical engineering. I resigned from the university two or three years ago after 12 years on the faculty. While doing research we had a breakthrough that led to this combination of methodologies, which led to a commercial product. That's how we started the company.
The core technology was done at the university under National Science Foundation and DARPA funding. Also SUNY had a packaging research consortium sponsored by IBM and other companies. Initially the problems presented to us especially by IBM were in the area of high speed packaging analysis. That's how we first encountered these problems. Through working with engineers and researchers at IBM we made this breakthrough. They said while that's good, our engineers really need tools not just methodologies. With their encouragement I decided to pursue the commercial implementation.
How did you get the intellectual property from the University and the consortium?
Actually the University applied for and received patents in the mid nineties. Sigrity has an agreement with SUNY. Sigrity has exclusive rights for the life of the patents. We pay royalties to SUNY.
Tell me a little bit about your company.
Sigrity was founded in 1998. It is privately held. We have R&D center in Shanghai. In the US we have about 27 people. China has 13 or so. So we have 40 people in total. China started only a year ago. We expect to grow very fast there.
Our main focus is high speed design issues for packaging. That's our initial product target. We are also targeting IC. Signal integrity and power integrity is our main focus. As speeds go higher, signal quality, power stability and power integrity become major concerns. In the early years our main customers were leading edge companies in microprocessors, graphics chips and communication chips. Companies like Cisco and Broadcom in communication and computer companies like Intel, IBM, HO and Compact.
I'm the president, Raymond Chen is Vice President and Teo Yatman is VP of Business Development and International Sales. David Chen of Cooper & Chen is on our Broad of Directors. We started the company with two people. We began in the PCB arena and then moved to IC like Cooper & Chen. Our new release at this DAC is in the co-design space. Co-design is chip and package together. At this moment we really address power analysis, dynamic power analysis. We see that the voltage spike gets lower and lower and the voltage margin gets smaller and smaller. Also with flip chip technologies, ICs and packaging become more closely interdependent, they are coupled with each other, and they
interact with each other. Most EDA tools only address the chips. Ninety percent of them only address the IC. They do not do the package. We are from the board and package space. We perform simulation analysis for leading edge packaging. For example, a major microprocessor company is our customer.
We have two markets. One is IC only and the second is chip on package. Nowadays especially with flip chip technology, if the power and noise distributions are determine separately for the chip and the package, they will not be accurate, If you ignore the package you will not get the correct noise distribution. That's why we have developed CoDesign to analyze the entire chip together with the whole package. Others like Synopsys or Cadence say that they have chip-package products but these are have only loosely integrated. They have a package design data base and a chip design data base and they try to share these databases. We have close integration. We analyze the entire structure.
That's out main approach and that's our main difference.
Our Speed2000 tool has been used for many years for packaging. For analyzing ICs we use XcitePI. These tools work in tandem at each time step to take into account the interaction with the structures, simultaneously simulating the entirety. With that approach people are more likely to get more accurate spatial distribution of the noise distribution and therefore they can make better decisions about how to design the power and grid efficiently; where to place capacitance and how large a capacitance to place. For all these different decisions you first need information on how large the noise is and how it is distributed.
Teo: Some of our customers are facing the problem that they have done the chip analysis and it seems to work. The package guys have designed the package and separately analyzed it. Then the chip goes into the package and there are performance issues. The thing that is missing is really looking at the critical interactions between the chip and the package. You can't just use a simple lumped RLC model for the package to really access the various interactions going on. As Jiayuan mentioned with flip chips you have thousand of bump contacts on the die that causes interactions to occur. You get noise propagation from one end of the chip going thru the package planes and appearing on
another side of the chip that you would not be able to recognize if you didn't have this cosimulation capability. This addresses a unique set of problems.
What is the output of this product? Does it help to diagnose the cause of the problem?
The output would be the spatial variation of the noise. From that you can know in which location you exceed the noise margin. For example, if there is a 1 volt power supply, the noise margin might be 50 milivolts. People can simulate different operations of the chip to find which locations exceed the noise margin. They can perform what-if analysis. If I redo the floor plan what will the noise margin be? If I put more capacitance, where should I put it and what will be the impact in terms of noise reduction? Will it meet the noise requirement?
Teo: You can run multiple simulations. You can actually see graphically where the hot spots are, where there are noise concerns. The solution may be to put a certain decoupling capacitance at the chip level or at the package level. Some people examine the options from more capacitance on the chip or more on then package. Which has more impact and how much. The CoDesign platform allows you to do a direct comparison to see how to place the capacitance and how to change the power structure to meet the design criteria.
What are you announcing at this DAC?
We announced CoDesign Studio last month. We started demonstrating it here at the show and plan to release it next month.
Is this product entirely new?
We have had the individual products within CoDesign Studio for a number of years. Speed2000 has been successfully used by a number of companies. The XcitePI tool was introduced last year at DAC. We started shipment of that tool at the end of late last year. This year we have put them together to enable cosimulation.
What is the packaging and pricing?
CoDesign Studio, basically the enabler of cosimulation, starts at $30K. The pricing for the individual tools is around $30K on an annual fee basis for Speed2000 and double that for XcitePI. We have various licensing modes. Those prices were for node locked. A shared license is much more expensive.
Have most of your existing customers purchase both Speed2000 and XcitePI?
Most of our existing customers are from the packaging and board space. A lot of semiconductor firms like the processor companies, top tier firms, the “IBMers” if you will. Companies designing their own packages or have design reference boards for their customers. They have relied on Sigrity to perform packaging and board analysis. These are the same customers who come to us and say: “We need some help on the IC side. We have noticed that packaging effects are going to impact our IC power capability. We need Sigrity to help us solve the problem of the package chip integration and interaction.” Some of these customers have the individual tools. If so,
they need only buy CoDesign Studio and they are all set.
Will this product open up new marketing opportunities for Sigrity?
We expect opportunities to come form both directions, from the packaging and board side and from the IC side. Packages are getting more complex and their costs are driving higher. At some point they are going to be more expensive than the actual die cost. The impact of the package design on the performance of the chip is becoming a very critical aspect of overall system performance.
You have R&D groups in China. How difficult is this to manage?
Actually we have three groups. As we recruit people the group managers will contract with each person individually. Their first few tasks are mainly to augment or supplement what we already have. Two or three people work together. We have not found it as difficult as some people would say to manage people overseas. Once we have people and each group needs more, we hire them.
Why overseas R&D? Lower cost, available talent, intent to sell there?
The EDA market in China is not so big so far. Perhaps it will be a few years in the future. Right now we have development resources there at a very good cost.
Cost aside, could you recruit the needed talent in the US with the required skills?
Cost is definitely less in China. Also in China there is a plentiful supply of talent. Each year they graduate 250,000 electrical engineers, a considerable supply for entry and midlevel engineers. Even putting cost aside, the amount of available talent makes it compelling to locate our R&D effort there.
What is the source of your funding?
We had initial funding from the NSF. Since then we have been funded by sales revenue. We are profitable, a privately held company growing at a very fast rate. We are pleased about the company's growth. I think that this particular segment of EDA is becoming more and more of a concern for a larger and larger number of customers. The technology is definitely driving the customers in the direction of needing solutions to these kinds of issues.
Whom do you see as possible competitors?
There are a lot of companies that claim to be doing analysis at the chip level. All of the big three and a few others do that. They do extensive chip level analysis. Very few companies do package analysis to any appreciable extent. Sigrity's strength comes from the packaging and board side. The extent of electromagnetic analysis capabilities with Sigrity's tools far surpasses what other companies have in terms of packaging.
Are some end user applications better suited to these tools than others?
Digital semiconductors, graphics and communications. Any high speed application that is driving simultaneous switching noise. There are other companies that address other segments of the market. Our forte is really in high speed digital design and the noise that is generated by high speed signals.
How is the demand for these products in terms of geography?
Teo: North America remains the strongest. Japan comes in second. Asia is really emerging and Europe is slower to move. But we are starting to see a lot more activity in Europe. We are generally pleased by the balance of our international and domestic business.
Is Europe trailing because Sigrity is below critical S&M mass or because of the way Europeans approach these issues?
Both. We have a direct channel sales force in North America. It's a very technical sale. Our sales forces tend to be very technical. They interact with engineers directly. That level of interaction is important to get customers to become comfortable with our solution. But our reps out in the international markets have been with us a number of years and they have come up to speed very nicely in terms of technical strength and support. Japan is particularly strong. NEC, Sony and Toshiba are major customers that are well supported and use our tools extensively there.
How do you convince prospects that your products works like you say they do? Success stories, six month evaluations, ..?
There are certainly customers that want to do an evaluation. It's not a six month process, more like a 30 day process for a typical evaluation. We have a number of success stories. These come not from something that we have written or ghosted for the customers but technical papers that have been written by our customers, really to teach other designers about how they are using the tools. These have appeared at various conferences and in various publications like IEEE, ECTC and EPEP. There is a list on our website. It really validates our solution. This is a great testimony for us because they have been written by our customer unsolicited.
Looking especially at the package and board area there are very few solutions out there that can address the extent of problems that we can. Anyone who is doing leading edge design in high speed digital space is going to be looking at tools for signal integrity and power analysis.
Is the product targeted at signal integrity groups or at the typical designer?
Some of the larger companies actually have teams of signal integrity engineers that are looking at SI issues specifically. That's obviously a great fit for us. More and more deign engineers are looking at having to solve SI problems. Larger companies have more resources and are developing very specialized teams that look at signal integrity and power integrity specifically and especially co-design by chip designers and package designers. Some of our customers are looking at teams that can bridge the gap between the two instead of throwing the chip over the fence to the package designers. They are finding out that they really need to simulate different structures simultaneously, to
assess the interaction.
In the area of packaging are there any new challenges?
Flip chip is one of the complicated structures. It seems to exhibit more of the interaction between the chip and the package. We just heard at the EDA business forum about multiple packages and silicon-in-package becoming the next level in complexity. These complex structures are definitely going to play a major role in power and signal integrity issues.
Are there any challenges to you software developers to keep up with these new technologies?
The more complex the structure the more robust the software needs to be.
What is the basis technology underlying the analysis?
For each structure (IC, package, board, card,
) we are looking for special geometric features for that structure. We customize meshes. The core includes customized electromagnetic analysis. It is not a general purpose methodology or approach. We explore geometric features. In chips and packages these include vias, planes and traces. The challenge is how to solve these kinds of structures more efficiently and for much larger capacity.
I had an opportunity recently to follow up my DAC interview with a phone conversation with Teo Yatman
How long have you been at Sigrity?
I've been here a little over 4 years now. For the EDA industry that's pretty long.
What's your role at the company?
My role is business development and international sales. I started as VP of Sales but we really needed some focus on business development. Our president wanted me to help the company in terms of visibility in the marketplace and partnerships with EDA players, am more active role with partners and major customers. I also manage international sales directly. There is a director of sales here that I work with closely. He handles the direct sales in North America. It's a small company so we tend to do a lot of things. I do a little bit of marketing PR activity. But as we grow we are definitely looking to add resource in marketing. We have had a direct sales team on board for a few years
now: We have an office here I Santa Cruz. A couple of years ago we opened in office in Boston and this year we opened an office in Austin, Texas. This will be the steady state in North America for a while. Internationally, I have reps in Germany, Israel, India, mainland China, Taiwan, South Korea and of course Japan. That keeps me pretty busy.
What challenges does having international reps present so far from headquarters present?
The major challenge for our reps is that our solutions are very technical in nature. We typically address the higher end of the market for high speed design be it package or be it board and now we are getting into chips. Having technical support in the field internationally has been a challenge. We've been very focused on making sure that we've hired the right kind of rep who has the customer relationships to help the business side and also a team of application engineers, the technical resources that can help support the customer because we expect the first tier support to be out in the field. We in turn support the reps of course but not the customers directly internationally. We
expect them to be the support channel for our customers. A lot of our tools come from an electromagnetic background if you go back to the beginnings of our company with our founder, Jiayuan Fang, at SUNY Binghamton. Electromagnetics is sort of the backbone of our company. We need to find people and there are not a lot of people out there who know this space very well. Japan has done very well, Asia also. Europe is a more slowly developing market. Our challenge now is to expand. Our next expansion will be in Europe.
Still with third party reps?
Yes, although we are definitely reaching a point in some areas where it makes sense to consider going direct in terms of ensuring our growth, especially as we are moving to new markets with CoDesign Studio product. We may determine that a direct presence is better suited for the future.
CoDesign was introduced a little before DAC. What has been the response?
We introduced the product in May. The response has been very good. We actually have several customers signed up for evaluations and hopefully purchases soon thereafter. Very active opportunities in the works in Japan, a major semiconductor company there. In Germany and several accounts in the US. There are probably a half dozen opportunities we are working on right now with CoDesign Studio. We are hoping that it's going to be a great product for us down the road because the nature of the problem is quickly getting to where chip analysis is of itself not adequate. They've got to take into consideration the package effects. We see more and more that it is becoming an issue at major
companies. We feel that we are in a great position to address that problem with our solution set.
Where does the product fit into the design flow?
Two places! One is in the pre-layout planning phase which clearly gives the customers a lot of what-if capability, being able to look at different type of packages and power configurations and to optimize that during the pre-layout phase. Also more or less a signoff in the post layout phase once the chip and package have been laid out, you can run the analysis tool to see the interaction between the two.
What does one vary during the pre-layout phase?
It could be the power plan or it could be decoupling capacitors to be palaced on the chip, the package or even on the board. But most of our customers are looking at the chip-package interface.
With our EDA partners we are positioning this capability in major IC flows such as Synopsys, Cadence and Magma. The first two are our partners. We try to work very closely, especially with customers using their design flows, to find out how to best optimize that capability.
You can run simulations of different packages to see the effect it has particularly in the power delivery network. This is a major area we are looking at.
We work closely with Amkor who is a major package supplier. They had a press release announcing that they would be working with us to come up with a template where customers can enter in different design parameters. They would then come back with a package configuration and they could simulate that with our Speed2000 tool. We are working on multiple fronts. Working with EDA players like Synopsys and package suppliers like Amkor. We are also in discussions with folks like TSMC to address the whole reference flow question.
Amkor is a major supplier of packages for a lot of fabless companies that are not designing their own packages. Amkor will do the package design. They will supply different package configurations that will meet the customer requirements. The key here is that we can analyze different package configurations and do what-if considerations of those packages, optimizing the package and chip power delivery performance. The whole idea is to be able to avoid costly respins down the road.
What we found with major customers is that they feel that they've got the package side down separately and the chip side done separately. But when they put it all together, problems come up in the power delivery system. We are trying to avoid those sorts of surprises after the fact and give customers the opportunity to analyze the electrical performance of the power delivery system. That's the whole idea behind CoDesign Studio.
Have these fables companies been flying blind in terms of their package selection?
Companies would have a list of criteria that that they would provide to let's say Amkor and say here is the kind of chip and here is the kind of package we need. Help us with the package design. The templates available for package design.
We can simulate them so that the customer has an opportunity to select the best package for his design. We are trying to give them a look ahead as early as possible in the design cycle.
Is there any change in methodology or training required to use this tool?
More and more especially the higher end customers have got teams of people working on power delivery systems for both chip and packages. They have to know about the chip, they have to know about the package. No more over the fence kind of thing. I'm done with the chip, go find the right packaging. The chip and package people have to work closer together. There is definitely a bit of cross training involved with this CoDesign solution. If we are going to put this in the hands of a chip designer, he will have to understand a bit more about package design and vice versa. More and more teams are being cross trained. Intel is an example. They have teams of people working on power
delivery systems. There is a lot more education being done between chip and packaging teams. Customers realize that they need to make this happen because it is not working the other way. It's not isolated design teams anymore.
There are two main issues in power tools. One addresses power delivery performance, that's where we come in, the other is low power which is another ballgame all together. We don't play in the low power arena. Golden Gate, whom you wrote about last week, is a player there. They mentioned Sequence who is in power analysis.
What is your definition of power performance?
The performance of power delivery system is making sure that you have clean power from the sources to the devices, making sure that you've minimized noise and that there is no noise corrupting the power delivery system.
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