October 14, 2002
Apache Unveils Next-Generation Power Integrity SOC Tool
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Ann Steffora - Contributing Editor

by Ann Steffora - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Apache Design Solutions released Tomahawk-S, a next-generation power integrity solution for voltage drop, electromigration, and power analysis of current and future SoCs. SoC designers can run multiple iterations in a single day on massively hierarchical designs using the tool, saving weeks when compared to traditional methods, Apache asserted. The company claims that the tool's performance, accuracy and ease-of-use is what enables the tool to convergence on an optimized physical power grid early in design.
Tomahawk is driven by a single-kernel architecture that supports power analysis, network extraction, reduction, and simulation, providing orders of magnitude in speed improvement over existing multi-kernel approaches, the company said. Based on extensive customer benchmarking, Tomahawk-S processes over four million gates in 10 minutes, leading to runtimes of less than one hour for large 25 million gate designs. Tomahawk's embedded one-step hierarchical database promises to eliminate the inaccuracies associated with traditional “black-boxing” or the “block-by-block” abstraction approaches of handling designs with different levels of abstraction. Apache said Tomahawk-S
is the first product in its lineup of physical design integrity analysis and simulation tools for power, timing and system I/O.

In other product news, Emulation and Verification Engineering (EVE), SA integrated ZeBu, its emulation platform, with SystemC, the leading C-based design language. The integration was demonstrated in the Xilinx Booth, at the recent SAME (Sophia Antipolis forum on Micro-Electronics).

The company's president and CEO Luc Burgun, believes that since SystemC appears to be the de-facto leader in the C-based design language war, SystemC's customers have now a compelling reason to adopt this design validation technology as they will be able to speed up the verification cycle by several orders of magnitude compared to existing technologies, and still enjoy full visibility into the design at run-time.

Built on a PCI board, ZeBu ZV-6000 introduces a breakthrough and proprietary interface, called Reconfigurable Test Bench (RTB) that connects the design-under-test to the test environment providing for exceptional throughput. The design-under-test is emulated via two Virtex II XC2V6000 devices, augmented by 128 MBit of SRAM memory, which collectively support a design capacity of more than one million ASIC gates. Through the RTB, SystemC models co-simulate at the signal-level through SystemC communication port reaching 70K cycles per second. Whereas, SystemC models co-simulate at the transaction-level through the channel communication class at several million of cycles per second, a
performance never claimed by any emulator or accelerator. Further, the revolutionary RTB allows access to any internal signals of the design-under-test without compiling the internal probes, EVE said.

Synchronicity, Inc. and Summit Design integrated the Synchronicity Developer Suite design collaboration and management solution with Summit's Visual Elite. Together, the tools allow ASIC and FPGA developers to collaborate on design definition and verification, even across multiple sites, while supplying the information project managers need to ensure project success.

The integrated tools are currently in use at MBDA France to develop system-chips combining unique and high-value functional blocks. MBDA's design teams use Visual Elite to specify, simulate and debug designs, while using DesignSync to manage design data from the beginning of the design process through to physical implementation in its geographically dispersed locations. Consistent data views are available to all designers, regardless of their location.

Additionally, the companies have integrated the design management tools found in the Developer Suite, DesignSync, into the Visual Elite user interface. Visual Elite provides IC and system designers with a comprehensive environment to capture design concepts graphically and textually to verify design behavior. DesignSync makes design data available to the entire project team, no matter where they are located. The other component of the Developer Suite, ProjectSync, enables multi-site project tracking, communications and collaboration.

More news from Summit Design: The company began shipping Visual Elite 3.0 to customers, right on time. The new version, that was announced just before DAC 2002 supports System C 2.0, VHDL, and Verilog. It is being shipped with FASTC, Summit's high-performance RTL 'C'-based design language, as well. FASTC targets RTL design to accelerate simulation performance over conventional HDL and 'C' event-driven engines. FASTC blocks are integrated with other C/C++ and HDL blocks at any abstraction level and can be automatically mapped into synthesizable HDL code.

CoWare Inc. and Denali Software Inc. announced an integrated platform for simulating memory and optimizing memory system performance for SoC designs. Denali's MMAV verification intellectual property (IP) software is now integrated with the CoWare N2C system-level design environment. By using Denali MMAV memory models in the CoWare N2C methodology, designers have access to robust simulation models for virtually any commercial memory device.

During simulation, the models provide valuable performance metrics for the memory system, and automatically test for potential design bugs at the memory interface. The C-based models from Denali are integrated directly with CoWare N2C, providing a seamless simulation and verification environment for advanced SoC development.

People News

Alan Naumann, president and CEO of CoWare, has agreed to represent the Electronic Design Automation (EDA) Consortium on the Design Automation Conference (DAC) Strategic Committee. The committee defines the future direction of the 40-year old conference. In this role, Naumann will attend committee meetings and advise the committee on the EDA Consortium's position on DAC's future direction. Naumann was elected to a two-year term on the 12-member EDA Consortium Board of Directors in April 2002.

Jon Turino, known for his expertise in ATE and DFT/BIST, announced the immediate availability of consulting services in the areas of product design for test strategy, ATE and BIST marketing strategy development, market studies and customer surveys, and a host of collateral services including brochure, data sheet and press release development.

“By taking advantage of out-sourced project or per diem based consulting companies can begin or complete projects that have been put on hold, or reluctantly abandoned, due to the massive reductions in fixed salary costs that have occurred over the least year in the semiconductor equipment and related businesses,” Turino explained. “The increasing shift from functional (or performance) test strategies to structural (or defect-oriented) methods, particularly at wafer probe and burn-in, has created new opportunities for SoC and ASIC designers to contribute to lower test costs throughout the semiconductor manufacturing process. It is also presenting opportunities for both
existing and new ATE vendors to introduce low cost IC engineering validation and production test systems for DFT and BIST enabled designs. Thus IC design and test teams may need help in arriving at the most cost effective DFT and BIST implementations. And ATE and BIST IP vendors supporting such strategies may benefit from outside help in getting their messages across.”

Services range from DFT/BIST implementation consulting to article, application note and white paper development. E-Mail:

InnoLogic Systems, Inc. appointed Yukari Chin to senior director of marketing. In this position, Chin will be responsible for establishing and directing the company's strategic initiatives, and increasing the market awareness for InnoLogic's products. Chin brings over 13 years of EDA industry experience in marketing management and applications engineering. Prior to joining InnoLogic, Chin served as director of marketing for Axis Systems, Inc., where she was responsible for developing corporate positioning and communications strategy for the company and its products as well as product management of new verification products. Earlier, she was a product marketing manager
for various products at Synopsys, Inc. and served in marketing and applications engineering management roles at IKOS Systems, Inc. (now Mentor Graphics). Chin began her career as an ASIC designer at Hughes Aircraft. She holds a Bachelor of Science degree in Electrical Engineering from Oregon State University.


Inovys Corporation has partnered with Q-star Test of Belgium to develop advanced IDDQ test capability for its Ocelot DFT Test System. Q-star Test NV will provide advanced quiescent-current measurement technology; custom integrated modules, and related intellectual property. Inovys will integrate these modules into its Ocelot DFT Test System. With an independent IDDQ measurement unit per device power supply, this will provide the Ocelot Test System the capability to concurrently perform high-speed IDDQ tests on up to thirty-two test sites.

Xilinx Inc. has joined IMEC's new industrial affiliation program (IIAP) that focuses on technology for reconfigurable systems. Xilinx is the first organization to join the IIAP. Through this program, IMEC will be applying its expertise in design technology for reconfigurable computing platforms to Xilinx FPGAs.

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-- Ann Steffora, EDACafe.com Contributing Editor.


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