February 07, 2011
Real Intent – Part II
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| by Russ Henke - Contributing Editor
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When the first EDA WEEKLY article on the Sunnyvale, CA EDA software vendor Real Intent was posted by this writer on October 11, 2010, the Company became only the second privately-held EDA enterprise featured in this EDA WEEKLY series that began on November 09, 2009:
With HQ in Palaiseau, France, EVE was the first privately-held EDA company featured, in “ALL ABOUT EVE” on April 26, 2010:
After Real Intent Part I appeared, Portland OR-based Lynguent became the third privately-held EDA entity featured, via a two-part sequence on November 15, 2010 and on December 13, 2010:
In this February 07, 2011 issue, we re-visit Real Intent (knowing full well that EVE will soon be seeking an encore as well).
Real Intent Sunnyvale CA HQ Building
Introduction to Real Intent Part II
The original article on Real Intent may be viewed at the following URL:
That another article on Real Intent might be in the cards, was revealed in this statement in the 1st write-up, ”It became clear during this delightful session with the Real Intent management on August 24, 2010 that there is a lot more to discuss with the people of the Company. It is very possible that a future EDA WEEKLY article will be devoted by this writer to Real Intent.”
Indeed, during the introductory interviews by the writer with Real Intent representatives in August, the discussions were focused on the business history of Real Intent, on its founders, and on several other key people both on the board of directors and inside the Company. For reasons of space limitations, however, the technology and product history of the Company were mentioned only in passing. Accordingly, a later edition of the EDA WEEKLY was planned to fill that gap; this is that article!
While the Company's founders, Dr. Prakash Narain and Mr. Rajiv Kumar serve as CEO and COO of Real Intent, respectively, both also enjoy the great good fortune of remaining deeply involved in the core development of Real Intent's technologies and thereby continue to be equally passionate about the elegance and effectiveness of the solutions that Real Intent brings to the IC design & verification community.
Dr. Narain Mr. Kumar
Herein we will focus on Real Intent's chronological progression through its first, second and third generation of products, so that readers can get a feel for the growth and advantages of Real Intent's underlying technology, and thereby understand one of the main reasons why Real Intent has been successful through the economic downturns of the last decade that have negatively affected many other startups.
In addition to Dr. Narain and Mr. Kumar, to develop this Part II article the writer also depended on conversations with others inside and outside the Company, most named and a few unnamed. In particular, the writer worked closely with Dr. Jin Zhang, Director of Technical Marketing, who first joined Real Intent in 2000. Dr. Zhang's detailed profile was included in the first article on Real Intent posted October 11, 2010. Thank you, Jin!
Dr. Jin Zhang
Real Intent's 1st Generation Technology Solution - Verix
When Prakash and Rajiv started Real Intent (then called 'Validity Design Automation') 12 years ago, their founding premise was 'to develop and market easy-to-use software products that verify, at the earliest opportunity in the design cycle, that a silicon chip's design actually implements the designer's intent.'
The Company achieved just that within two years! On July 4, 2000, Real Intent announced that it was shipping Verix, its first generation solution, which analyzes a chip design's RTL (Register Transfer Level) description, extracts the Implied Design Intent, and verifies the design against the Implied Intent using exhaustive formal sequential techniques (News release at
In the balance of this article, numbered Footnotes
are used to designate references, and such Footnotes
are collected at the end of the article}.
Verix detects bugs in the design and generates a VCD (Value Change Description) trace to assist debugging, all without the need for a testbench (according to Wikipedia, a testbench is a virtual environment used to verify the correctness or soundness of a design or model). Since chip designers don't need to develop testbenches to run it, Verix can be used as soon as RTL is written, therefore allowing bugs to be found more easily and as a result, significantly reducing the design and verification cycle of a chip.
There you have it - the founding premise of Real Intent.
Verix Intent Driven Verification System
NVIDIA was among the first companies to have adopted Verix. According to Chris Malachowsky, Founder and VP of Engineering of NVIDIA (Santa Clara, CA):
“Given the complexity and sheer size of our 3D processors, effective design verification enhances our ability to deliver products on time. We use Verix to find and eliminate errors early in the design cycle, even before the first testbenches are built. With the combination of its low learning curve and its high coverage and capacity, Verix quickly became a valuable part of our verification methodology. Intent-Driven Verification applied hierarchically across a full-chip's functionality promises to revolutionize design verification.”
“All sounds great, but what is 'implied intent' exactly? And how do you actually know what the designer's implied intent is without talking to him?”
Well, the idea is actually quite simple. Say a person wants to jog. The thought of jogging is an expressed intention. To achieve that, all the parts of her body have to cooperate and move synergistically together. Though she never expresses a clear intention of moving her legs, arms and body in a certain way, the intention for how each part of her body should move is implied from the expressed intention of jogging.
For RTL designs, a piece of RTL code might be to implement an arbiter (arbiters are electronic circuits that allocate access to shared resources) so that's the expressed intent of the design. To achieve that, each part of the RTL code has to work together in the right way. If there is dead code in the design, or if a state in the state machine (a state machine is a behavior model composed of a number of states, transitions between those states, and actions) is unreachable, then the design may not function correctly as an arbiter or whatever else the design is intended to be.
So what Verix does is to analyze the RTL design to make sure that each part of the RTL constructs, such as definitions, assignments, blocks of code, state machines, and pragmas (a pragma is a directive communicating additional implementation-specific information), etc., exhibit certain desired behavior in order for all these parts to work together to implement a meaningful functionality.
“If Verix examines each language construct, how is it different from Lint?” (Lint is a type of EDA tool that performs simple checking on RTL designs to catch potential coding errors).
The 'use model' of Verix is indeed very similar to a Lint tool, since only design files are needed to run Verix, which made its adoption easy. The differences lie in the types of behavior analyzed, the underlying technology used, and the depth of analysis.
Lint typically performs simple checks on the design to look for coding issues, sort of like spelling/grammar checker in MS Word. It's a much simpler technology and it can usually be developed in a 6 to 9 month time frame.
Verix, sometimes referred to by its customers as 'Formal Lint' or 'Smart Lint,' goes way beyond that. It employs formal technology and performs deep sequential analysis to detect bugs that will not be detected by Lint tools.
For example, the following piece of RTL code will pass a 'linter' cleanly; however, Verix reports a dead code on Line 8, which is clearly not what the designer intended it to be. The dead code revealed a coding error which would be much harder to detect using other techniques, such as simulation, since only after exhaustively simulating all possible vectors can dead code be confirmed. Verix detects this easily because of the benefit of the underlying exhaustive formal technology. In that sense, Verix is like an editor, looking for complex grammatical errors, rather than merely identifying
simple spelling errors in an article.
The founders of Real Intent were justifiably proud of this early work because they were the first to apply formal property checking techniques automatically. Formal property checking used to require truly expert users spending a lot of time writing assertions in order to use the tools. With Verix, everyday users could and do take advantage of the power of formal property checking (exhaustive proof & counter example generation) without the need to spend any extra effort setting things up to run the tool, and/or even fully understanding how it works
under the hood. Verix brought out significant productivity gains in the design & verification flow, so much so that automatic assertion generation and verification have since become part of the offerings from other companies, such as Mentor 0-In Formal Verification, Cadence IFV and Synopsys Magellan.
For Dr. Narain and Mr. Kumar, it was no small achievement to pioneer the field of automatic formal verification and set the standard for the industry to follow. It was also therefore no surprise that Verix was awarded the “2000 Product of the Year” by the Electronics Product Magazine (Footnote )
Product of the Year Aware by Electronics Product Magazine
“Formal techniques have long held the promise of revolutionizing RTL verification of large complex ICs. However, two problems have withheld the realization of the dramatic benefits of these techniques - ease of use and capacity. Real Intent has made key advances on both fronts", so said Real Intent President and CEO Prakash Narain at award time. "Our latest improvements remove the biggest hurdles in realizing the benefit of formal RTL verification. Our breakthrough allows our customers to continue to leverage their investment in Verix as design complexity increases."
And customers agreed. According to Eric Demers, Engineering Manager at ATI (ATI merged with AMD in 2006), “Verix has been invaluable to us as the first verification tool that we run on our RTL designs. It easily catches a host of design bugs that have traditionally been hard to find in simulation or have taken significant verification cycles to detect. Verix has allowed us to shorten our simulation time by eliminating most common bugs one encounters with new RTL. We are pleased that Real Intent has built a great formal ABV product, and we have come to reply upon
it for our graphics projects."
Ads Used for “Got Verix” Marketing Campaign (2001)
Verix 2000 was Only the Beginning
Real Intent kept on developing the technology and expanding its applications in Verix in the following years. Here are just some of the highlights:
On March 12, 2001, Verix added VHDL support (VHDL stands for VHSIC Hardware Description Language, where VHSIC stands for Very High Speed Integrated Circuit) (Footnote ). This enabled Verix's adoption by design houses using VHDL language for RTL designs.
On May 21, 2001, a hierarchical formal methodology that automatically combines the formal results of lower blocks to formally verify higher blocks, was introduced (Footnote ). This was an important breakthrough because traditional formal technology, due to its exhaustive nature, can only be applied to block level designs. The hierarchical formal methodology engineered by Real Intent enabled scalable formal RTL verification at higher level of the design hierarchy, thereby enhancing the ability of the tool to catch more complex and deeper bugs in the design.
Hierarchical Formal Methodology
On May 28, 2002, Real Intent added formal Clock Intent Verification (CIV) to Verix (Footnote ). Recognizing the ever increasing complexity of clock distribution networks in the IC designs, Real Intent was the first company to target Clock Domain Crossing (CDC) verification using automatic formal technology.
With the knowledge built to understand a design's implied intent, Verix CIV is built to understand the clock intent by automatically identifying the clock domains within the design and the signals crossing the clock domains. It also identifies the absence or presence of synchronizers at the clock domain boundaries, and determines assertions that can exhaustively verify the data transfer stability across the clock domain boundaries.
Verix CIV started off on solid ground with the experiences Real Intent gained with Verix Implied Intent. This in turn built a great foundation for Real Intent's later success of Meridian CDC as the acknowledged best product in the industry performing CDC verification.
Verix Clock Intent Verification
Cooperation with Others
While Real Intent has created a core competency in automating formal property verification and making it easy to use for mass design and verification engineers, it has also cooperated with and leveraged the expertise developed by other EDA companies to provide end users with the best overall products. For example, technologies from Verific Design Automation (
) and SpringSoft (then Novas) (
) have been incorporated into Real Intent
's tool suites to provide front-end Verilog and VHDL language parser and back-end debugger.
Real Intent has also been keen on making its products easier to fit into existing chip design and verification flows, by interpolating with tools from other entities. This philosophy is manifested in many decisions made by the Company, as can been seen from some of the following developments.
By 2005, Verix had been adopted by over 35 companies such as NEC, ATI, SiCortex, and Micronas.
The year 2005 was also a critical point in Real Intent's corporate history. The company raised $6.5 million in financing (Footnote ) and added several new executives to the team, including Dr. Pranav Ashar as the CTO of Real Intent (Footnote ).
The additional funding also allowed more resources to be added to the team on many other fronts and enabled further development of its Implied Intent, Clock Intent and Expressed Intent technologies.
Verix 5.0, released on December 12, 2005, achieved even greater performance & capacity breakthroughs with its new formal Convergence Engine (Footnote ).
The Second Generation of Products from Real Intent
Real Intent's 2nd Generation of Technology Solutions was characterized by the term, “EnVision”.
On March 8, 2005, Real Intent extended the application of formal technology to implementation, by introducing a new functionality to verify timing exception accuracy (Footnote ).
Instead of adding this new functionality to Verix, a new product called PureTime was introduced. PureTime verifies timing exceptions - false paths and multiple cycle paths - in a Synopsys Design Constraint (SDC) file to make sure they are correct, as faulty timing exceptions can cause chip re-spins and failing hardware in the field. When there is a violation, a counterexample is generated to show how the violation could happen, just like in Verix.
It was a conscious decision by Real Intent not to add this functionality to Verix. While the Real Intent team had kept on improving Verix over the previous 5 years, they felt that it was time to separate Verix into different products so that each can be architected to best suit the requirements and needs of different applications.
The re-architecture and redesign resulted in the introduction of Ascent and Conquest on July 03, 2006 (Footnote ) as well as Meridian on April 16, 2007 (Footnote ):
Ascent is the extension of Verix Implied Intent Verification. Ascent represented a significant step forward in automatic formal verification. Its redesigned architecture was solely focused on automatic checks that are derived from the RTL designs, thereby offering greater flexibility and performance. It supported both PSL (Property Specification Language) and SVA (System Verilog Assertion) constraints as they become the standard assertion languages in the industry. Also new with Ascent was Ascent SimPortal, which links to dynamic simulation using simulators by other EDA companies such as Synopsys to
offer added verification confidence.
Conquest is the extension of Verix Expressed Intent Verification with improved performance and capacity by incorporating new proof engines.
Meridian is the extension of Verix Clock Intent Verification. Based on experiences learned in the previous 5 years, recognizing the ever increasing complexity of clock and reset architecture in SoC (System-on-chip) designs, Real Intent re-engineered its approach to CDC verification by incorporating multiple strategies in order to achieve CDC signoff:
The first strategy is structural analysis. By analyzing the structure of the design (at RTL or gate level), Meridian can automatically extract its clock intent and perform analysis to report risky structural constructs, such as potential glitches in asynchronous control crossings (control signals going from one asynchronous clock domain to another) or on clock propagation path, as shown in the examples below.
The second strategy is automated formal analysis. While structural analysis can report potential risky circuit constructs, it cannot prove conclusively that the data transfer interface between asynchronous clock domains is reliable. The Meridian metastability-aware formal engine automatically formulates properties on each data & control crossing and performs exhaustive proof to make sure that the crossing interface is robust against a metastability effect. If a condition is found that could lead to unreliable circuit behavior, a counter-example will be generated, illustrating the exact conditions which could happen,
as shown in the example below showing a highlighted gray-encoding violation:
The third strategy is Meridian's SimPortal capability that allows users to leverage existing simulation infrastructure created to perform functional verification to do CDC verification. Meridian generates simulator monitors and checkers that can be plugged into the simulation testbench easily. This provides additional confidence and allows users to signoff on CDC verification at the chip level.
Ascent, Conquest, Meridian and PureTime together made up the EnVision family of products from Real Intent. With a light-weight infrastructure, experiences gained from Verix customer engagements, and the new formal engine driven by formal technology expert Dr. Pranav Ashar as CTO of Real Intent, the EnVision family of products was, when introduced, leading edge in automatic formal, assertion based verification, clock domain crossing verification as well as timing exception verification.
With solid product offerings, Real Intent pushed on to global sales by appointing Ms. Carol Hallett as Vice President of Sales in December 2007 (Footnote )
Real Intent added a K.K. office in Japan in April 2008 (Footnote ), a distributor in Israel in March 2009 (Footnote ), and a distributor in South Korea in August 2010 (Footnote ).
During 2000 to 2010, Real Intent was also very active in participating industry tradeshows, seminars, and conferences to promote these products.
The Third Generation
While Real Intent was eminently successful with its first and second generations of products, Dr. Narain and Mr. Kumar never stopped pushing the technology limit and venturing into new applications brought forth by the need of designing and verifying today's large and complex SOC chips.
As Real Intent celebrated its 10th year of business in EDA in 2009, Prakash again took the company on the journey of retooling. As Prakash wrote in his 8/20/2010 blog, “The 10 Year Retooling Cycle” (well actually in Real Intent's case, its own retooling cycle is every 5 years) “There may be fewer EDA companies these days, but innovation is still going strong. Products for the next 10-years are available and getting adopted. Precise Lint tools with blazing performance are available. Precise CDC tools make it possible to achieve reliable sign-off on today's designs. New
innovations are underway for solving complex issues such as X-Optimism and X-Pessimism in simulation. Automatic Formal Analysis tools quickly improve design quality with minimal effort. SDC tools ensure the effectiveness of time consuming STA efforts. The 10-year retooling cycle is in effect again”.
And that's exactly what Real Intent has done in the last year - retooling its products to welcome the challenges for the next 10 years. That brings us to Real Intent's 3rd generation of technology solutions.
Real Intent's 3rd Generation Technology Solutions - Ascent, Meridian and PureTime
Recognizing the emerging market needs, in 2009 Real Intent expanded its product portfolio to several key areas by adding lint, X-Verification, Design-for-test (DFT) and constraints management solutions. Given the brand equity established with its second generation products Ascent, Meridian and PureTime, Real Intent decided to leverage these brands to introduce the following product families:
Real Intent Product Families
Ascent Lint, added to the family in January 2010, offers low-noise and high-performance linting (Footnote ). As Dr. Pranav Ashar stated, “Richer HDLs and billion-gate designs have combined to create the need for next-generation linters that understand language semantics and common programming idioms and do more than just syntax checking, all the while still delivering the high speed expected of a linter.”
Existing linters that started out 10 years ago are known for generating large reports that are humanly impossible to parse and for taking a long time to run at the whole chip level. Real Intent, with its roots in the hard formal technology, can easily extend its expertise to lint checking required for today's billion gate designs. Ascent Lint is unique in the industry in terms of delivering this combination of speed, comprehensiveness and configurability.
Ascent Lint Flow Chart
Ascent IIV, which is basically the second generation Ascent product with improved functionalities.
Ascent XV for X-Verification, which detects X-related bugs efficiently in RTL.
Ascent ABV, which is basically the second generation Conquest product rolled under the new Ascent family.
Meridian CDC, which is based upon the second generation Meridian product with several major improvements and releases in the last 2 years. Meridian CDC version 2.5 released in May 2009 added shell model support for hierarchical analysis, enhanced RAM support and formal analysis of FIFO, improved structural and formal reporting as well as GUI debugging capabilities (Footnote ). Meridian CDC version 3.0 released in March 2010 added many new features such as several new check categories related to reset uncertainty, reset propagation, pseudo constants and encapsulation, it also introduced industry
only frequency-independent formal analysis which allows comprehensive CDC verification without clock frequency constraints (Footnote ).
According to a recent survey to understand how customers view Real Intent and other companies' solutions, all of the respondents rated Meridian CDC as “better” or the “best” CDC tool compared to competition. As stated by one of the respondents, “You guys are great. Awesome support. You guys always want to do things right and do it best”. “Do it right and do it best” has been the spirit of Real Intent and it is reflected in Meridian CDC. The next Meridian CDC release coming out in a few months, the writer was told, would have even greater and exciting features.
Meridian CDC Flow Chart
Many customers rave about Meridian CDC's superior performance and accuracy:
Linming Jin, Director of ASIC PD at Brocade Inc. “Brocade uses Meridian CDC in the design flow to ensure correct clock domain crossing operations. Meridian CDC helped us find scenarios where we missed synchronization, and has also detected glitches in vendor's IP we purchase. It is easy to use. Real Intent has excellent technical support.”
Inwan Choi, Director at Anagran Inc. “Meridian CDC has been a very useful tool in our verification flow. It uncovered many clock crossing issues in our FPGA designs and allowed us to confirm that the fixes were valid. We are pleased with Meridian CDC's superior technology, comprehensive coverage and high performance”.
Peter Teng, Sr., Engineering Manager at NEC (now part of Renesas) “Of all the Clock Domain Crossing (CDC) tools NEC evaluated, Real Intent's Meridian has the least number of false CDC errors (if any at all). Its setup on the clock and reset environment is painless, as it identifies the clock and reset relationship automatically, requiring almost no setup effort from the designer. Meridian is high performance, finishes CDC analysis in minutes. Meridian greatly simplifies designer's task in CDC verification.”
Meridian DFT, introduced in May 2010, identifies DFT trouble spots at RTL to allow designers to optimize testability (Footnote )
PureTime Constraints, first introduced in August 2009 (Footnote ) and further enhanced in Nov 2010 (Footnote ), includes constraints checking, equivalency checking between two constraint scenarios, coverage analysis of single as well as multi-mode designs, and template generation.
PureTime Exceptions, which is basically the second generation PureTime product with improved functionalities.
PureTime Family Flow Chart
Concluding Remarks: Defining Principles
When the writer asked Dr. Prakash Narain what in his view makes Real Intent's solutions better than competition, Prakash replied modestly, “It pays to learn hard lessons in life early. In the early years of Real Intent when we were focusing on harnessing the power of formal technology and automating it to make it easy to use for mass designers, we learned a lot about how to extract the real intent of the designs for complete and accurate analysis, how to optimize the formal analysis engines for high performance, how to simplify the user interface and reporting
for maximum productivity, and how to architecture the tool flow to enable signoff.
Over the years we have accumulated lots of knowhow and applied these techniques to different applications. For example, Meridian CDC (formerly Verix CIV) has been used in production flows at many companies and has helped tape out thousands of complex designs in the last 8 years. The ultimate goal for our customers is to be able to sign-off on CDC verification. Therefore we have adapted our philosophy and approach to CDC verification based on some basic principles:
We require more thorough environment setup because this provides the necessary safety net and confidence that CDC analysis will be accurate and complete so our users can sign-off on CDC verification at the end; A setup-lite approach taken by our competitions can leave holes in CDC verification and nasty surprises late in the cycle;
We identify root cause of CDC issues and only report that rather than all the symptoms of it so that users don't have to be faced with huge report with lots of noise. It is impossible to sign-off when one can't even go through and examine each line in the report;
Our structural and formal analysis are based on actual design principles rather than design templates, therefore Meridian CDC can handle more diverse designs styles;
We offer a layered approach to CDC verification in multiple levels.
Extending all the knowledge learned to simple applications such as linting and constraints management is a much easier task. Compared to other companies which started with simple technology like linting and now are trying to extend their solutions to formal, they are having a much deeper learning curve and are faced with a much harder task to conquer. We benefitted from climbing the tallest mountain early when we were younger and had no fear. Now we can stand high, see farther and go farther. I think that's our strength”.
Just as Dr Zhang and the writer were completing this EDA WEEKLY article, Real Intent released news about its performance:
Real Intent Reports Stellar Revenue Growth of Over 80% in 2010
SUNNYVALE, California - January 25, 2011 -
Real Intent, Inc
., the leader in automating the intelligence of formal techniques for design verification signoff, announced today that the company's revenue in 2010 increased more than 80% when compared to 2009. In addition, the company's customer list grew by over 50%, adding major semiconductor companies in storage, computing, networking, communication and consumer electronics industries.
Prakash Narain, CEO of Real Intent, remarked, “Real Intent has seen strong growth for the last several years despite the difficult economic conditions. Ever-increasing design complexity has driven the market growth for Real Intent's products. In addition, our technical superiority in performance and accuracy as well as our excellent customer support has enabled us to displace our competitors at several large semiconductor accounts.”
Real Intent news
included announcements of new releases of Ascent™, Meridian™ and PureTime™ as well as a new product, Meridian DFT. The company also signed a Korean distributor and added Masahiro Fujita as a Technical Advisor.
During the first half of 2011, Real Intent will showcase its leading signoff technology at many worldwide events:
Tokyo University Seminar
, Tokyo, Japan, February 2, 2011
Design Verification Conference (
), San Jose, CA, March 1-2, 2011
Synopsys Users Group (
), Santa Clara, CA, March 28-30, 2011
Real Intent and SpringSoft Joint Verification Seminar, San Jose, CA, April 21, 2011
, Tel-Aviv, Israel, May 3-4, 2011
48th Design Automation Conference (
), San Diego, CA, June 5-8, 2011
About Real Intent
is the leader in automating the intelligence of formal techniques for electronic design verification signoff. Real Intent's
, Meridian and PureTime software families dramatically improve functional verification efficiency and design quality for ASICs and FPGAs devices and are used by design and verification teams worldwide.
Georgia Marszalek, Valley PR LLC for Real Intent, +1-650-345-7477,
Notes to editors:
Ascent, Meridian and PureTime are trademarks of Real Intent, Inc.
All other trademarks and trade names are the property of their respective owners.
After the last six months of getting to know Real Intent, its people, culture, technology and the journey it has taken over the last 10 years, what Prakash says does not seem boastful at all, but rather statements of fact.
Just as one of the motivational posters that Real Intent hangs on its office walls says, “Real Intent continues to see beyond the current formal verification solutions”.
Real Intent has indeed gone a long way in its technology journey to provide best-in-class solutions to the design and verification communities. This writer looks forward to seeing that leadership translated into Real Intent's continued growth and ongoing technology breakthroughs in the years just ahead.
News release on Verix winning “Product of the Year” award
News release on Verix adding VHDL support
News release on Verix adding hierarchical analysis capability
News release on Verix adding Clock Intent Verification capability
News release on Real Intent raising $6.5M funding
News release on Pranav Ashar joining Real Intent as CTO
News release on Real Intent achieving additional milestones in Verix development
News release on Real Intent adding Timing Exception Verification to its product suite
News release on Real Intent announcing Ascent and Conquest at
News release on Real Intent announcing Meridian
News release on Carol Hallett joining Real Intent
News release on Real Intent opening a K.K. office in Japan
News release on Real Intent adding distributor in Israel
News release on Real Intent adding distributor in Korea
News release on Real Intent adding Lint to its portfolio
News release on Real Intent releasing Meridian CDC version 2.5
News release on Real Intent releasing Meridian CDC version 3.0
News release on Real Intent announcing Meridian DFT product
News release on Real Intent announcing PureTime Constraints product
News release on Real Intent releasing PureTime version 3.5
On February 01, 2010, this writer published the first of what became two major EDA WEEKLY articles about Santa Rosa CA based Agilent EEsof EDA, the leading supplier of electronic design automation software for high-frequency and high-speed system, circuit, and modeling applications.
While Agilent EEsof's financials have not been routinely published separately from those of the overall Agilent Electronic Measurement Group in which Agilent EEsof resides, the EDA industry generally acknowledges Agilent EEsof's market leadership position in annual revenue generation in its Radio Frequency (RF) niche.
The second EDA WEEKLY article on Agilent EEsof appeared on March 29, 2010.
These two articles may be viewed at the following URL's:
February 01, 2010 Part I
March 29, 2010 Part II
Now, on to ONE YEAR LATER:
Given the ongoing economic difficulties many companies have endured over the last twelve months, this writer was especially interested in how Agilent EEsof has fared during that period, and in what changes might have taken place within the enterprise.
Any concern was completely unwarranted. This writer discovered that Agilent EEsof experienced one of its best years thus far, and it ended the year with the best revenue quarter in its history!
“Our customers are definitely designing their ways out of the recession,” observed Todd Cutler, Marketing Senior Manager of Agilent EEsof. “Designing new products and/or products for new markets are proven means to position a company for success as the economy improves. To do that, you need effective and modern design tools, and we are grateful that customers are choosing Agilent EEsof more than ever before.”
Considering the number of new innovations in its own software over the past year, it seems EEsof has been following its own mantra. Agilent EEsof's fastest growing new business is in the area of electronic-system-level (ESL) design. In January 2011, Agilent EEsof announced the industry's first commercially available LTE-Advanced product, an Agilent SystemVue design library. The new system design library, an option to Agilent's SystemVue 2011 software, is available today. Wireless system architects and chipset makers working to provide the 4G network 1-Gbps peak download speed can now use Agilent's
W1918 LTE-Advanced library for earlier verification of physical layer (PHY) algorithms and system performance.
Agilent also saw its business volume double in the area of electromagnetic simulation (EM). Agilent now offers all three major types of EM simulation technologies: (1) Method of Moments for 3D planar structures, (2) Finite Element (FEM), and (3) Finite Difference Time Domain (FDTD) for full 3D structures.
Agilent's EMPro 3D EM product offers both FEM and FDTD and enables designers to analyze a variety of structures from high-speed connectors to handset antennas. “Our 3D planar and FEM EM simulators are fully integrated in the ADS platform,” commented Charles Plott, Product Marketing and Planning Manager for Agilent EEsof. “Customers value the productivity they gain by working in a single integrated environment.”
Business in the high-speed digital design area also reached record levels, led by the introduction of IBIS-AMI model generation and simulation. The rapid growth of multi-gigabit digital links has caused designers to “hit the microwave wall” and to stop thinking of chip-to-chip signals as a stream of ones and zeros. This creates the need for actual signal integrity design tools that are accurate at microwave frequencies, which plays to Agilent's strength.
Agilent's introduction of X-parameters* to model non-linear circuits turned heads the previous year, and this year EEsof has added this capability to both SystemVue, its ESL design software for system architects and algorithm developers, and to Genesys, its low-cost, EDA software for RF/microwave circuit board and subsystem designers.
X-parameters have created a discontinuity in the design world, according to Mark Pierpoint, Agilent EEsof's new vice president and general manager. “Generating nonlinear behavioral models from simulation can reduce simulation time by a factor of more than 100,” Mark said. “Major amplifier vendors worldwide have discovered the benefit of measuring, modeling and simulating using X-parameters.”
Advanced Design System 2011
The blockbuster story of the past twelve months, however, occurred in September 2010, when Agilent EEsof began unveiling details of the highly-anticipated next release of its flagship RF design software, Advanced Design System 2011. ADS 2011 will provide users breakthrough capabilities for multi-technology design inherent in advanced RF System-in-Package (SiP) components. Two years in the making, ADS 2011 includes true multi-faceted RF design, which enables co-design with combined technologies (board, laminate, package, module, and IC), and it boasts a use-model that makes EM simulation far easier
for every engineer.
The Advanced Design System (ADS) 2011 delivers many exciting new features for all ADS users with new capability for multi-technology co-design like that inherent in RF modules and system-in-package (SiP) designs. ADS 2011 builds upon the recent ADS releases, expanding Agilent's complete MMIC/Module desktop flow to deliver the industry's leading, complete, integrated, end-to-end product realization RF design solution.
Sunglasses may be required:
So with the release of ADS 2011 imminent, with new capabilities and improvements for all ADS users, and after a year of releasing improvements in every product in its product line, the future surely appears bright for EEsof ONE YEAR LATER.
“There are clear opportunities for further growth as we apply more of Agilent's engineering and measurement technology to solve customer challenges” concluded Pierpoint.
Note: We are grateful to those Agilent EEsof EDA persons named above who participated in this ONE YEAR LATER update, along with Kirt Kisling of Agilent, who is today Marketing Programs Manager.
"X-parameters" is a trademark of Agilent Technologies, Inc. The X-parameter format and underlying equations are open and documented. For more information,
About the Writer:
Since 1996, Dr. Russ Henke has been and remains active as president of HENKE ASSOCIATES, a San Francisco Bay Area high-tech business & management consulting firm. The number of client companies for Henke Associates now numbers more than forty. During his corporate career, Henke operated sequentially on "both sides" of MCAE/MCAD and EDA, as a user and as a vendor. He's a veteran corporate executive from Cincinnati Milacron, SDRC, Schlumberger Applicon, Gould Electronics, ATP, and Mentor Graphics. Henke is a Fellow of the Society of Manufacturing Engineers (SME) and served on the SME International Board of Directors.
Henke was also a board member of SDRC, PDA, ATP, and the MacNeal Schwendler Corporation, and he currently serves on the board of Stottler Henke Associates, Inc. Henke is also a member of the IEEE and a Life Fellow of ASME International. In April 2006, Dr. Henke received the 2006 Lifetime Achievement Award from the CAD Society, presented by CAD Society president Jeff Rowe at COFES2006 in Scottsdale, AZ. In February 2007, Henke became affiliated with Cyon Research's select group of experts on business and technology issues as a Senior Analyst. This Cyon Research connection aids and supplements Henke's ongoing, independent consulting practice (HENKE ASSOCIATES). Dr. Henke is also a
contributing editor of the EDACafé EDA WEEKLY, and he has published EDA WEEKLY articles every four weeks since November 2009; URL's available.
Since May 2003 HENKE ASSOCIATES has also published a total of ninety-three (93) independent COMMENTARY articles on MCAD, PLM, EDA and Electronics IP on IBSystems' MCADCafé and EDACafé.
Further information on HENKE ASSOCIATES, and URL's for past Commentaries, are available at
. March 31, 2011 will mark the 15th Anniversary of the founding of HENKE ASSOCIATES.
You can find the full EDACafe event calendar here
To read more news, click here
-- Russ Henke, EDACafe.com Contributing Editor.