February 07, 2011
Real Intent – Part II
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Russ Henke - Contributing Editor


by Russ Henke - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


The Second Generation of Products from Real Intent


Real Intent's 2nd Generation of Technology Solutions was characterized by the term,
“EnVision”.


On March 8, 2005,
Real Intent extended the application of formal technology to implementation, by introducing a new functionality to verify timing exception accuracy (Footnote [8]).


Instead of adding this new functionality to Verix, a new product called
PureTime was introduced. PureTime verifies timing exceptions - false paths and multiple cycle paths - in a Synopsys Design Constraint (SDC) file to make sure they are correct, as faulty timing exceptions can cause chip re-spins and failing hardware in the field. When there is a violation, a counterexample is generated to show how the violation could happen, just like in Verix.


It was a conscious decision by Real Intent not to add this functionality to Verix. While the
Real Intent team had kept on improving Verix over the previous 5 years, they felt that it was time to separate Verix into different products so that each can be architected to best suit the requirements and needs of different applications.


The re-architecture and redesign resulted in the introduction of
Ascent and
Conquest on July 03, 2006 (Footnote [9]) as well as
Meridian on April 16, 2007 (Footnote [10]):


Ascent


Ascent is the extension of Verix Implied Intent Verification. Ascent represented a significant step forward in automatic formal verification. Its redesigned architecture was solely focused on automatic checks that are derived from the RTL designs, thereby offering greater flexibility and performance. It supported both PSL (Property Specification Language) and SVA (System Verilog Assertion) constraints as they become the standard assertion languages in the industry. Also new with Ascent was Ascent SimPortal, which links to dynamic simulation using simulators by other EDA companies such as Synopsys to
offer added verification confidence.


Conquest


Conquest is the extension of Verix Expressed Intent Verification with improved performance and capacity by incorporating new proof engines.


Meridian


Meridian is the extension of Verix Clock Intent Verification. Based on experiences learned in the previous 5 years, recognizing the ever increasing complexity of clock and reset architecture in SoC (System-on-chip) designs,
Real Intent re-engineered its approach to CDC verification by incorporating multiple strategies in order to achieve CDC signoff:
  • The first strategy is structural analysis. By analyzing the structure of the design (at RTL or gate level), Meridian can automatically extract its clock intent and perform analysis to report risky structural constructs, such as potential glitches in asynchronous control crossings (control signals going from one asynchronous clock domain to another) or on clock propagation path, as shown in the examples below.




  • The second strategy is automated formal analysis. While structural analysis can report potential risky circuit constructs, it cannot prove conclusively that the data transfer interface between asynchronous clock domains is reliable. The Meridian metastability-aware formal engine automatically formulates properties on each data & control crossing and performs exhaustive proof to make sure that the crossing interface is robust against a metastability effect. If a condition is found that could lead to unreliable circuit behavior, a counter-example will be generated, illustrating the exact conditions which could happen,
    as shown in the example below showing a highlighted gray-encoding violation:






  • The third strategy is Meridian's SimPortal capability that allows users to leverage existing simulation infrastructure created to perform functional verification to do CDC verification. Meridian generates simulator monitors and checkers that can be plugged into the simulation testbench easily. This provides additional confidence and allows users to signoff on CDC verification at the chip level.



  • Ascent, Conquest, Meridian and PureTime together made up the EnVision family of products from Real Intent. With a light-weight infrastructure, experiences gained from Verix customer engagements, and the new formal engine driven by formal technology expert Dr. Pranav Ashar as CTO of Real Intent, the EnVision family of products was, when introduced, leading edge in automatic formal, assertion based verification, clock domain crossing verification as well as timing exception verification.







    With solid product offerings,
    Real Intent pushed on to global sales by appointing
    Ms. Carol Hallett as Vice President of Sales in December 2007 (Footnote [11])





    Ms. Hallett



    Real Intent added a K.K. office in Japan in April 2008 (Footnote [12]), a distributor in Israel in March 2009 (Footnote [13]), and a distributor in South Korea in August 2010 (Footnote [14]).


    During 2000 to 2010,
    Real Intent was also very active in participating industry tradeshows, seminars, and conferences to promote these products.







    The Third Generation


    While
    Real Intent was eminently successful with its first and second generations of products, Dr. Narain and Mr. Kumar never stopped pushing the technology limit and venturing into new applications brought forth by the need of designing and verifying today's large and complex SOC chips.


    As
    Real Intent celebrated its 10th year of business in EDA in 2009, Prakash again took the company on the journey of retooling. As Prakash wrote in his 8/20/2010 blog, “The 10 Year Retooling Cycle” (well actually in
    Real Intent's case, its own retooling cycle is every 5 years) “There may be fewer EDA companies these days, but innovation is still going strong. Products for the next 10-years are available and getting adopted. Precise Lint tools with blazing performance are available. Precise CDC tools make it possible to achieve reliable sign-off on today's designs. New innovations are underway for solving complex issues such as X-Optimism and X-Pessimism in simulation. Automatic Formal Analysis tools quickly improve design quality with minimal effort. SDC tools ensure the effectiveness of time consuming STA efforts. The 10-year retooling cycle is in effect
    again”.


    And that's exactly what
    Real Intent has done in the last year - retooling its products to welcome the challenges for the next 10 years. That brings us to
    Real Intent 's 3rd generation of technology solutions.




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    -- Russ Henke, EDACafe.com Contributing Editor.


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