August 02, 2010
High Level Synthesis Has Come Of Age
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Cadence is one of the three largest EDA vendors in our industry. Its products cover the entire design flow process, and thus also high level synthesis. Its product is, may be not very creatively, called
C-to-Silicon Compiler, conversationally referred to a
"C2S". This tool is part of the Encounter family of products. Michael McNamara, a pioneering entrepreneur in high level synthesis, is now Cadence VP and GM in charge of this product line.
Cadence states that C2S delivers competitive results in part due to the product architecture that allows parallel optimization of both control and datapath logic. Users can also take advantage of the ability of performing incremental synthesis and to reuse the design across multiple applications and process technologies.
Power consumption has become a major concern in the design of electronic products. This is not the case just for portable devices, but heat generated by compute farms and switching stations is also a problem to be confronted. Heat means loss of energy to electronics, and that, in turn means that either battery life is shorten, or that additional energy must be used for cooling purposes. Both scenarios are undesirable. It has been demonstrated that a major source of power savings derives from appropriate system design, and thus minimizing power consumption when transforming a system design into RTL is an important goal.
Chipvision is a German company dedicated to doing just that. The company was established in 2002 as a spin off of the OFFIS research and development institute for information technology tools and system of the Carl Von Ossietzky University of Oldenburg. Chipvision Design Systems, also founded in 2002 addresses the North American market. Prof. Dr.-Ing. Wolfgang H. Nebel, world-renowned technologist and academician, is co-founder, chairman and chief technology advisor of ChipVision. Since June 2005 he also has served as chairman of OFFIS. Wolfgang is very active in EDA standardization activities as well.
The company's product is
PowerOpt, architected to address the design for low power issues by supporting designers in generating power efficient RTL circuits from C, C++, and SystemC descriptions. The resulting RTL descriptions are in Verilog. The tool optimizes algorithms, data path bit widths, resources, memory accesses, memory configurations, voltage and performance, clock gating and interconnects. The solution also implements leakage power optimizations. Power constraints for logic and physical synthesis are output in Common Power Format (CPF) and Unified Power Format (UPF).
Using the tool, designers can trade off between energy consumption, area and performance of a circuit and compare the different synthesized architectures to choose the optimal one.
standard. After leaving Chronologic he was a co-founder of CynApps a company that merged with Chronologic in early 2001. The resulting entity was named Forte Design Systems.
In 2009 Forte acquired Arithmatica that developed and marketed
CellMath Designer, a datapath synthesis tool, and the CellMath IP library.
Cynthesizer to strengthen its ability to handle datapath designs.
Impulse Accelerated Technologies is based in Kirkland, Washington. The company was founded by Brian Durwood and David Pellerin. Prior to Impulse Mr. Durwood was a Vice President at MaxteK, a Tektronix subsidiary, while Mr. Pellerin was the products architect at Accolade Design Automation, a company he had founded. Impulse, therefore, has roots in the Northwest, a region that has strong credential in both the semiconductors and EDA industries.
The company states that the product,
CoDeveloper, is best suited to applications solving image and video processing, digital signal processing, data compression and encryption, and hardware accelerated computing. The tool is specifically designed to support FPGA based designs that target FPGA accelerated architectures. It accepts C code and, using its software-to-hardware compiler, and interactive parallel optimizer, and target platform specific information, generates FPGA programming files specific to the chosen target device. If the user chooses a central processing unit that the FPGA interfaces with, CoDeveloper also produces the host/FPGA interfaces, and links to the CPU APIs.
Mathworks is a company that does not specifically focus on EDA, yet it serves the EDA market with both of its two main product families: MATLAB and Simulink. Mathworks, which recently changed its corporate name from the previous "The Mathworks", was founded by Jack Little and Cleve Moler. MATLAB was the first product. The M- language combines the features of Fortran and C with added math and graphics functions. The language, and the tools associated with it have been used by engineers for DSP algorithm and filters design for years. Designers can now use
Filter Design HDL Coder to generate both synthesizable Verilog and VHDL code from a MATLAB design.
Simulink is the other product family that allows designers to simulate dynamic and embedded systems in various application areas. When working in the electronics domain, engineers can use
Simulink HDL Coder to generate bit-true, cycle accurate, synthesizable Verilog and VHDL from Simulink models, Stateflow Charts, and Embedded MATLAB code. In addition Cadence, Mentor, and Synopsys have worked with Mathworks to build co-simulation environments that allow the concurrent execution of their system simulators with Simulink. The environment allows architects and designers to follow a true model-based design methodology.
Mentor Graphics entered the synthesis market relatively late in comparison to Cadence and Synopsys. But, building on its considerable presence in the design simulation and verification markets, has established a strong position in ESL, including in high level synthesis. Its product,
Catapult C can be used for both ASIC and FPGA designs. Originally the product accepted only C or C++, but lately Mentor has introduced support for SystemC as well.
The tool has a graphical interface that helps designers easily choose the target process, setup constraints, and the RTL output: either Verilog or VHDL. Catapult C is well integrated with ModelSim, so that designers can verify the produced code versus the original code. Catapult C has a companion product,
Catapult C Library Builder that allows engineers to build design libraries that can contain technology specific operators, memories, and function blocks.
Synopsys, a company built on synthesis technology that has grown to become the largest provider of EDA solutions in terms of revenue, could not be absent from the HLS market. The acquisitions, first of Synplicity, and lately of Synfora's technology has given further boost to Synopsys capabilities. The company calls the family of products
Synphony, a name you would expect Springsoft would use instead. I found that Synopsys' web pages are a bit misleading and confusing. If you look hard enough you will find that Synphony is not the only HLS product sold by the company.
Synplify DSP also falls in this market sector.
You can find the full EDACafe event calendar here.
To read more news, click here.
-- Gabe Moretti, EDACafe.com Contributing Editor.