August 02, 2010
High Level Synthesis Has Come Of Age
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Gabe Moretti - Contributing Editor


by Gabe Moretti - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


Cadence is one of the three largest EDA vendors in our industry. Its products cover the entire design flow process, and thus also high level synthesis. Its product is, may be not very creatively, called
C-to-Silicon Compiler, conversationally referred to a
"C2S". This tool is part of the Encounter family of products. Michael McNamara, a pioneering entrepreneur in high level synthesis, is now Cadence VP and GM in charge of this product line.


Cadence states that C2S delivers competitive results in part due to the product architecture that allows parallel optimization of both control and datapath logic. Users can also take advantage of the ability of performing incremental synthesis and to reuse the design across multiple applications and process technologies.


Power consumption has become a major concern in the design of electronic products. This is not the case just for portable devices, but heat generated by compute farms and switching stations is also a problem to be confronted. Heat means loss of energy to electronics, and that, in turn means that either battery life is shorten, or that additional energy must be used for cooling purposes. Both scenarios are undesirable. It has been demonstrated that a major source of power savings derives from appropriate system design, and thus minimizing power consumption when transforming a system design into RTL is an important goal.


Chipvision is a German company dedicated to doing just that. The company was established in 2002 as a spin off of the OFFIS research and development institute for information technology tools and system of the Carl Von Ossietzky University of Oldenburg. Chipvision Design Systems, also founded in 2002 addresses the North American market. Prof. Dr.-Ing. Wolfgang H. Nebel, world-renowned technologist and academician, is co-founder, chairman and chief technology advisor of ChipVision. Since June 2005 he also has served as chairman of OFFIS. Wolfgang is very active in EDA standardization activities as well.


The company's product is
PowerOpt, architected to address the design for low power issues by supporting designers in generating power efficient RTL circuits from C, C++, and SystemC descriptions. The resulting RTL descriptions are in Verilog. The tool optimizes algorithms, data path bit widths, resources, memory accesses, memory configurations, voltage and performance, clock gating and interconnects. The solution also implements leakage power optimizations. Power constraints for logic and physical synthesis are output in Common Power Format (CPF) and Unified Power Format (UPF).


Using the tool, designers can trade off between energy consumption, area and performance of a circuit and compare the different synthesized architectures to choose the optimal one.


Forte is one of the early entrants in the high level synthesis market. John Sanguinetti is Forte's Chief Technical Officer. John has been active in computer architecture, performance analysis, and design verification for many years. He founded Chronologic Simulation in 1991 and was its President until 1995. He was the principal architect of VCS, the Verilog Compiled Simulator, and was a major contributor to the resurgence in the use of Verilog in the design community. Dr. Sanguinetti served on the Open Verilog International Board of Directors from 1992 to 1995 and was a major contributor to the working group which drafted the specification for the IEEE 1364 Verilog
standard. After leaving Chronologic he was a co-founder of CynApps a company that merged with Chronologic in early 2001. The resulting entity was named Forte Design Systems.


In 2009 Forte acquired Arithmatica that developed and marketed
CellMath Designer, a datapath synthesis tool, and the CellMath IP library.


Cynthesizer takes SystemC descriptions as input and generates optimized RTL Verilog code. Cynthesizer comes with a fully integrated automation system called the Behavioral Design Workbench. It automates the time-consuming task of writing makefiles and tool integration scripts. It provides dependency management and process automation to implement a complete high-level design and verification flow. The product also provides TLM synthesis that allows transaction level descriptions of algorithms to be synthesized. In this manner what is simulated is also what is synthesized. Although Forte still markets CellMath Designer, the technology is also being incorporated into
Cynthesizer to strengthen its ability to handle datapath designs.


Impulse Accelerated Technologies is based in Kirkland, Washington. The company was founded by Brian Durwood and David Pellerin. Prior to Impulse Mr. Durwood was a Vice President at MaxteK, a Tektronix subsidiary, while Mr. Pellerin was the products architect at Accolade Design Automation, a company he had founded. Impulse, therefore, has roots in the Northwest, a region that has strong credential in both the semiconductors and EDA industries.


The company states that the product,
CoDeveloper, is best suited to applications solving image and video processing, digital signal processing, data compression and encryption, and hardware accelerated computing. The tool is specifically designed to support FPGA based designs that target FPGA accelerated architectures. It accepts C code and, using its software-to-hardware compiler, and interactive parallel optimizer, and target platform specific information, generates FPGA programming files specific to the chosen target device. If the user chooses a central processing unit that the FPGA interfaces with, CoDeveloper also produces the host/FPGA interfaces, and links to the CPU APIs.


Mathworks is a company that does not specifically focus on EDA, yet it serves the EDA market with both of its two main product families: MATLAB and Simulink. Mathworks, which recently changed its corporate name from the previous "The Mathworks", was founded by Jack Little and Cleve Moler. MATLAB was the first product. The M- language combines the features of Fortran and C with added math and graphics functions. The language, and the tools associated with it have been used by engineers for DSP algorithm and filters design for years. Designers can now use
Filter Design HDL Coder to generate both synthesizable Verilog and VHDL code from a MATLAB design.


Simulink is the other product family that allows designers to simulate dynamic and embedded systems in various application areas. When working in the electronics domain, engineers can use
Simulink HDL Coder to generate bit-true, cycle accurate, synthesizable Verilog and VHDL from Simulink models, Stateflow Charts, and Embedded MATLAB code. In addition Cadence, Mentor, and Synopsys have worked with Mathworks to build co-simulation environments that allow the concurrent execution of their system simulators with Simulink. The environment allows architects and designers to follow a true model-based design methodology.


Mentor Graphics entered the synthesis market relatively late in comparison to Cadence and Synopsys. But, building on its considerable presence in the design simulation and verification markets, has established a strong position in ESL, including in high level synthesis. Its product,
Catapult C can be used for both ASIC and FPGA designs. Originally the product accepted only C or C++, but lately Mentor has introduced support for SystemC as well.


The tool has a graphical interface that helps designers easily choose the target process, setup constraints, and the RTL output: either Verilog or VHDL. Catapult C is well integrated with ModelSim, so that designers can verify the produced code versus the original code. Catapult C has a companion product,
Catapult C Library Builder that allows engineers to build design libraries that can contain technology specific operators, memories, and function blocks.


Synopsys, a company built on synthesis technology that has grown to become the largest provider of EDA solutions in terms of revenue, could not be absent from the HLS market. The acquisitions, first of Synplicity, and lately of Synfora's technology has given further boost to Synopsys capabilities. The company calls the family of products
Synphony, a name you would expect Springsoft would use instead. I found that Synopsys' web pages are a bit misleading and confusing. If you look hard enough you will find that Synphony is not the only HLS product sold by the company.
Synplify DSP also falls in this market sector.


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-- Gabe Moretti, EDACafe.com Contributing Editor.


Reviews:
Review Article
  • Re: High Level Synthesis Has Come Of Age August 02, 2010
    Reviewed by 'Zack63'

    You should have mentioned that some tools are true synthesis tools, while some of these are really "parametric blocks"  e.g. the tools from Matlab and Synopsys Module compiler, Synplify DSP are not true synthesis engines.  There is behind the scenes structures which are modified via parameters.


    Other tools e.g. Catapult, C2S, Forte, AutoESL, are true synthesis engines, where you can create arbitrary hardware from an input description + synthesis directives.


    Also, you should have mentioned that Catapult is the dominant C Synthesis tool for many years in a row.  Mentor was an early maker of High level Synethsis tools, not late to the market (they just didn't have an RTL synthesis tool other than the ones aquired from Silicon Compilers)





      2 of 2 found this review helpful.
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  • Sr PV Mgr August 02, 2010
    Reviewed by 'Stefen Boyd'
    The title grabbed my attention, but the typos and disorganized flow ended up leaving me disinterested and disappointed.


      One person of 3 found this review helpful.

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  • EDA Consultant August 02, 2010
    Reviewed by 'Daniel Payne'
    Gabe,
    Thanks for the overview.
    I worked at Silicon Compilers from 1986 through the Mentor acquisition. We never considered our tools High Level Synthesis rather it was an environment that had:
    * Many configurable logic blocks (SRAM, Datapath, Muliplier, IO Pads, Random Logic, ALU, etc.)
    * Place & Route
    * Floor Planning
    * IR Drop Analysis
    * Package editor
    * Cycle based simulation
    * Transistor-level static timing analysis
    * Logic Synthesis
    * ATPG
    * Schematic Capture
    The Genesil product line was dropped by Mentor, although the GDT product line along with Lsim lived a bit longer at Mentor.

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