Château de Brest Castle and Tour Tanguy on the River Penfeld in Brest
Walker Memorial - MIT Sloan School
Nassau Hall Princeton University
Other Key EVE Management Persons:
In addition to Dr. Burgun, Mr. Larzul, and Dr. Rizzatti, there are several other key EVE management members that should be mentioned here:
Mr. William Addi is EVE’s Chief Financial Officer. Prior to EVE, William served as CFO at companies in the software Application Service Provider (ASP) business and in retail industries, managing revenues in the hundreds of million of dollars. Mr. Addi started his career as a senior audit manager at KPMG in Los Angeles, Lyon and Paris, France, and he has worked at increasingly responsible international finance and management positions. Mr. Addi holds a master's degree in business administration from the Ecole de Management de Lyon, France (E.M. Lyon).
Mr. Addi is a member of the French Board of Chartered Accountants (Expert Comptable et Commissaire aux Comptes) and is a Certified Public Accountant (CPA) in California.
Mr. Ballan is Vice President of EVE Worldwide Operations. Prior to joining EVE, Mr. Ballan worked for ENEA, a provider of embedded software and services, where he most recently served as vice president of business development and previously as sales and operations manager for Europe and Asia. Previously, he worked as an organizational consultant and as the Central European sales manager for Wind River Systems, helping to grow the business in Central Europe to a significant portion of the company's revenues. He was part of Wind River's management during its initial public offering (IPO). Mr. Ballan is a graduate of École
Mr. Ballan also attended Chuo University in Japan as an exchange student. He attended the Stanford University Graduate School of Business-AEA Executive Program. Mr. Ballan is fluent in French, German, English and Japanese. Two Other EVE Founders: By the way, the two other founders of EVE in 2000 are Stephane Guerineau, software developer, and David Reynier, application engineer. Both are still at EVE and play key roles in their fields. Ron Burns OK, OK. I give up. This ain't makin' it! Guess those darn MSEE degrees mean something after all! Figure 1 - EVE bases its ZeBu emulation system around Xilinx FPGA's. Figure 2 - ZeBu uses one set of FPGA's for the device under test and another for the Reconfigurable TestBench (RTB). #### ####
The EVE USA Operation:
Since 2002, Lauro has carefully grown the EVE-USA operation from one to thirty-one today across the country. Headcount growth locally has necessitated moves within San Jose to increasingly larger offices; EVE-USA HQ is now located at 2290 North First Street.
San Jose-based VP Sales Ron Burns has multiple salespeople and fifteen applications engineers spread across the USA, six of whom operate out of San Jose.
Lauro also has three administrative support personnel, several in Marketing, and some nine R&D engineers who came from the acquisition by EVE of Tharas some years ago.
Like the rest of EVE, growth of EVE-USA over the last year has been carefully managed, owing to the impact of the worldwide economic recession. But until 2007, EVE had enjoyed a compounded revenue growth rate of 100%, so some slowing was inevitable.
EVE's Raison d'être:
OK, OK. Up to here in this article, with the exceptions of two brief mentions in the foregoing, the precise business EVE is in would be clear only to a handful of EDA and semiconductor insiders. Well, maybe more than a “handful”, but still operating in a niche known only to serious electronics specialists. Most readers would have to admit that heretofore, this article could have been describing the story of any one of multiple EDA startups around the world. So just what is EVE's raison d'être - its “reason for being”?
To be fair, please remember that in paragraph two (2) of the Introduction to this issue of EDA WEEKLY, the writer “disclosed” that EVE “occupies a niche in the esoteric world of EDA Hardware/Software Co-Verification, ASIC Emulation, RTL Emulation, Hardware Emulation, ASIC Validation, ASIC Prototyping and FPGA Prototyping.” I bet you're saying to yourself, “Yep, all that stuff is sure esoteric, all right!”
To describe further what EVE's accomplishments have been, and where it's going from here, requires a deeper understanding of its namesake, “Emulation Verification Engineering”. Actually, this name does provide hints to EVE's raison d'être. Each of the three words is in fact very descriptive of the EDA niche EVE serves. Really.
OK, here goes, courtesy of Wikipedia and “Electronic Design Automation For Integrated Circuits Handbook,” by Lavagno, Martin, and Scheffer:
The largest fraction of silicon integrated circuit re-spins are due to functional errors. Thus, comprehensive functional verification is key to reducing development costs and delivering a product on time. Functional verification of a design is most often performed using logic simulation software and/or prototyping. There are advantages and disadvantages to each and often both are used.
Logic simulation is (relatively) easy, accurate, flexible, and low cost. However, simulation is often not fast enough for large designs and almost always too slow to run application software against the hardware design. FPGA-based prototypes are fast and inexpensive. But the time required to implement a large design into several FPGA's can be very long and is error-prone. Changes to fix design flaws also take a long time to implement and may require board wiring changes. Since FPGA prototypes (usually) have little debugging capability, probing signals inside the FPGA's in real time is very difficult, if not impossible, and recompiling FPGA's to move probes takes too long. The usual
Simulation acceleration can address the performance shortcomings of (plain) simulation to an extent. Here the design is mapped into a hardware accelerator to run much faster and the testbench (and any behavioral design code) continues to run on the simulator on the workstation. A high-bandwidth, low latency channel connects the workstation to the accelerator to exchange signal data between testbench and design. By Amdahl's law, the slowest device in the chain will determine the speed achievable. Normally, this is the testbench in the simulator. With a very efficient testbench (written in C or transaction-based), the channel may become the bottleneck. In some cases, a
In-circuit emulation improves greatly on FPGA prototyping's long time to implement and change designs, and provides a comprehensive, efficient debugging capability. While it takes weeks or months to implement an FPGA prototype, it takes only days to implement emulation. And design changes take but a few hours or less. Emulation does this at the expense of running speed and cost compared to FPGA prototypes. Looking at emulation from the other direction, it improves on acceleration's performance by substituting "live" stimulus for the simulated testbench. This stimulus can come from a target system (the product being developed), or from test equipment. At 10,000 to 100,000 times
You're just going to have to take my word for it.
Better yet, let's listen to how Lauro Rizzatti positions EVE's business:
“Emulation technology has been around for over twenty years. The largest company (to manufacture and sell emulators) in the past was Quickturn, which was eventually acquired by Cadence. The second one was IKOS, which was acquired by Mentor Graphics. The problems with those early emulation implementations were multifaceted. They were expensive machines, in the millions of dollars range. So they were limited in terms of market acceptance. You had to be a big company to spend that sort of money. The other issue was that when you were deploying those emulators of old, you often had to provide an army of application engineers just to make the system work. So it was not only
“What EVE did at the time of its founding, was to identify an opportunity to implement a far less-expensive solution that would be easier to use and would require fewer engineers to deploy. That was difficult challenge, but that was the thinking behind EVE's ZeBu emulators: small, inexpensive and through extensive software (compiler and runtime software), easier to deploy without the need for that army of application engineers.”
“Said another way, EVE was and is driven by two basic criteria: (1) low cost (significantly lower than traditional emulators), and (2) high speed (significantly higher than traditional emulators). To address the first, EVE selected off-the-shelf FPGA's instead of designing custom chips, as done by rivals Today that choice by EVE has proved to be the right choice, since redesigning custom chips every two/three years (currently at 40nm), would be economic suicide when attacking a total market of less than $200 million. The second criterion stemmed from EVE's desire to move outside the traditional hardware emulation space, typically focused on hardware verification, to also
That captures it nicely.
In summary, EVE products significantly shorten the overall verification cycle of complex integrated circuits and electronic systems designs.
Now we are ready to talk more about the current state of EVE as well as about the future.
Looking Ahead: Optimism Abounds!
The entire EVE employee population is extremely optimistic going forward. First, EVE now has shipped over 300 ZeBu systems to over 60 customers, and EVE has some $30 million in annual revenue. According to company literature, EVE has become the acknowledged leader in Hardware/Software Co-Verification. Nine (9) of the top ten (10) semiconductor companies worldwide rely on EVE products to verify their SoCs (Systems-on-Chips). With the best ROI in the market, EVE products are also the choice of startups that need first-pass silicon success.
Further, EVE today sports a remarkable list of products. See for example:
Likewise, EVE has amassed a long list of Customer Success Stories. See for example:
See also Footnote  for Logos of current EVE Reference Customers.
Lauro Rizzatti's personal optimism was reinforced by his recent visits in early 2010 to India, Japan, Taiwan, Korea, China and France. He wrote about his two-month trip in a blog entry on April 5, 2010:
The EVE ZeBu-Server:
A huge reason for EVE's current optimism is thanks in no small measure to the recent success of EVE's latest product, the EVE ZeBu-Server , a scalable and affordable emulation system. (By the way, ZeBu means “zero bug”).
Introduced by EVE in mid-2009, the ZeBu-Server is a high capacity system emulator with the relatively easy setup and debugging associated with emulation, and the price/performance of rapid prototyping. Supporting multiple users, interfaces, and host computers, the EVE ZeBu-Server is an emulator with a capacity up to 1 Billion ASIC gates. The ZeBu-Server is primarily aimed at large-scale, multi-core chip and system emulation applications. It is ideal for the system-integration phase of the design cycle where multiple logic blocks, multiple chips, and embedded software all must be verified together.
Hardware design and software development teams can share the same system and design representation, and can readily collaborate when debugging complex hardware/software interactions. The net effect is that hardware/software integration takes place much earlier in the design cycle, thereby reducing silicon re-spins and accelerating time to market.
ZeBu-Server is hands-down the highest performance emulator in the market, while also offering the most cost-effective solution in the smallest footprint. This is because the ZeBu-Server has been architected to take advantage of the largest and latest generation of Field-Programmable Gate Arrays (FPGAs) in production.
The ZeBu compiler automatically handles any design, regardless of size, coding style, clocking scheme, or memory structure, making it easy to map very large designs. These have historically been the biggest problems with other FPGA-based rapid prototyping systems, but not with ZeBu, thanks to its complete software infrastructure.
Priced from $150,000, the Ze-Bu-Server offers automated, fast and incremental compilation from SystemVerilog, Verilog and VHDL register transfer level (RTL) code. It includes complete RTL signal waveform dumping and support for SystemVerilog Assertions.
On February 22, 2010, EVE announced that the ZeBu-Server had been selected from hundreds of nominations to be a finalist for this year's EDN Innovation Awards. ZeBu-Server was selected for the electronic design automation (EDA) Front-End Simulation and Database Tools category. This year's list of finalists features 32 categories and more than 120 products that shipped in volume in the 2009 calendar year.
To qualify, EVE demonstrated innovation that resulted in a significant advance in technology and product development with ZeBu-Server during the past 12 months. “We received an impressive number of submissions for our 2009 Innovation Awards program, indicating that innovation was alive and well despite the economically challenging year,” said Rick Nelson, EDN editor-in-chief. “EVE's ZeBu-Server was one of the outstanding submissions (that) our editors chose.”
What doe the ZeBu-Server look like?
The writer has waited till last to display an actual image of a ZeBu-Server, because it really does look just like the proverbial “black box”. Anyway, here goes:
(Note: If readers still long for a deeper understanding of the what and the why of the EVE ZeBu-Server, another enlightened explanation was provided by EVE's own VP Engineering Ludovic Larzul, in an article published in the Xcell Journal for Q3 2009 Issue 68 by Xilinx, Inc., entitled, “EVE Taps Xilinx for Multiple Generations of Emulators.” Excerpts from that article are included in Footnote  toward the end of this EDA WEEKLY article).
Today, EVE describes itself the worldwide leader in hardware/software co-verification solutions, including hardware description language (HDL) acceleration and extremely fast emulation. EVE products significantly shorten the overall verification cycle of complex integrated circuits and electronic systems designs. Its products also work in conjunction with popular Verilog, SystemVerilog, and VHDL-based software simulators from Synopsys, Cadence Design Systems and Mentor Graphics.
Here's another testimonial regarding EVE's leadership position; it was published offshore (from CYBERMEDIA INDIA ONLINE LIMITED - CIOL)
Tuesday, November 24, 2009
PARIS, FRANCE: EVE SA, headquartered in Palaiseau, France, is leading the design team acceleration and emulation market. In its latest report, titled Register Transfer Level Market Trends 2009, the market research company Gary Smith EDA, based in Santa Clara, California, the United States, said it has assessed the market share of EVE SA at 28 percent for 2008. According to Gary Smith EDA, EVE SA offers what many consider as the “true design team acceleration and emulation boxes”
Gary Smith EDA defines the design team acceleration and emulation market (as opposed to the verification team acceleration and emulation market) as “hardware-based verification solutions which fit on a designer's desktop and which do not impose restrictions on environmental conditions.” Gary Smith, founder and chief analyst of Gary Smith EDA, said in a commentary that designers need an emulation box in order to do any kind of software verification.
EVE SA, according Smith, have penetrated an array of fast-paced markets - including processors, multi-media, graphics, wireless, consumer electronics and communications. These segments demand high-execution speed, capacity, pricing, thorough and fast-design debugging, short-compile times, multi-user capabilities as well as scalability.
Lauro Rizzatti acknowledges that EVE still has to contend with competition in the marketplace, but most of it comes from either different emulation and verification techniques, or older hardware implementations. EVE serves a small but important sophisticated niche in a general worldwide electronic design automation (EDA) market which is already itself relatively small in the overall applications software marketplace. At the moment, new prospects for EVE products may call in one or more of the Big 3 EDA vendors (Synopsys, Cadence and Mentor), to make certain that they have done the required due diligence.
These vendors are of course not sitting idly by and watching EVE corner the market entirely.
For example, as recently as April 19, 2010 Synopsys introduced the HAPS®-60 series of rapid prototyping systems for complex SoC design and verification challenges. The HAPS-60 series, part of the Confirma™ Rapid Prototyping Platform, is a rapid prototyping system that enables early hardware/software co-verification and system-level integration. The HAPS-60 series uses Xilinx Virtex®-6 devices.
For its part, on April 15, 2010, Mentor Graphics announced that STMicroelectronics' Home Entertainment and Display group (HED) had adopted MGC's
But at the end of the day, if the ZeBu-Server and/or related EVE products fit the prospect's special needs, Lauro is confident of winning.
Indeed, Lauro elaborated quite clearly on his ecumenical view of the marketplace in a recent blog entry (February 22, 2010):
“Large companies (EDA vendors) have positive characteristics… they often have vast resources for marketing programs and their sales channels are much better developed and coordinated then a startup's. These same large companies carefully track the progress of a startup and can be counted on to acquire them, when the timing's right. This is all part of the EDA ecosystem that's worked for many years. Startup, emerging company, large established players. In an ecosystem such as EDA, we need both large suppliers and innovative small companies to keep driving and encouraging technological advances.”
This entire blog may be read at:
What's Next for EVE?
Lauro says that EVE is working on capabilities to increase the number of gates that ZeBu-Server can handle beyond the one billion mark. Surprised, the writer asked, “Who in the world needs more than a billion?” Lauro grinned sheepishly, “We already have customers whom we are not permitted to refer to by name, who are anxiously awaiting delivery of ZeBu's that handle four (4) billion gates simultaneously. Such systems will contain advanced, next-generation FPGA's from our partners, along with improvements in ZeBu software, the product development of which is already well underway.”
Asked about what the likely “exit strategy” currently is for privately-held EVE, Lauro reminded the writer that EVE investors are in no hurry. Likewise, the personnel at EVE are enjoying their respective careers these days.
But Lauro, the EVE executive team and BOD do have a game plan, of course. First, EVE would like to achieve increased annual revenue numbers. Then either an IPO or more likely the acquisition path would be pursued or responded to; candidates to acquire EVE are known to exist both in the USA as well as offshore, with some very interesting names coming from the Pac Rim.
 Footnote: The first EDA Weekly in the current series was devoted to,
 Footnote: Another enlightening explanation of the what and why of the EVE ZeBu-Server was provided by EVE's own VP Engineering Ludovic Larzul, in an article published in the Xcell Journal for Q3 2009 Issue 68 by Xilinx, Inc., entitled, “EVE Taps Xilinx for Multiple Generations of Emulators.” Excerpts from that article are included below:
Creating a hardware emulation system is no easy task. At a minimum, each generation of emulation system has to accommodate a growing number of logic gates, memory and DSP blocks to allow ASIC and ASSP system-on-chip (SoC) designers to debug their extremely complex devices before sending them off to the foundry for production. Emulation systems must also be easy to program, reliable and, what's more, affordable. Here at EVE, we've developed several generations of emulation systems-leveraging the power of Xilinx® FPGA's-to emerge as a leader in the market.
Today's SoCs are exceedingly complex pieces of silicon. They contain one or more processors that will execute software. The software code they run is every bit as important a part of the final system as the silicon itself. The software and the silicon have to act as a seamless solution; if there's a problem, it might be the software, or it might be the silicon.
Designers can only do so much software testing on a development host. No reasonable host development system can reflect the true parallelism of the target SoC. You can really only test out such issues as synchronization, data integrity and resource contention in situ, and that's far too late to identify problems. Simulation isn't a viable solution; it's simply too slow to allow the execution of any realistic code.
As a result, engineers have been using emulation systems for well over two decades to verify the most advanced ICs the semiconductor industry can build. Most of these earlier-generation emulation systems were powered by custom ICs that the emulator vendors designed themselves. They would then pass the cost of the custom IC development on to their customers, making the power of emulation more cost-prohibitive for companies struggling with ever-tighter IC development budgets.
In 2001, EVE broke with tradition by basing our innovative emulation system on Xilinx FPGA's. The goal was to provide the lowest hardware-assisted verification cost of ownership in the industry, as achieved through a combination of high execution speed, high capacity (which today means up to a billion gates), quick design revision, flexible and powerful debugging capabilities, lowest cost per gate and most cycles per dollar. In addition, we wanted to make the easy to use for ASIC designers who might not be familiar with FPGA design. The result was the ZeBu emulation system (Figure 1):
We've now developed six generations of emulators, the most recent of which is ZeBu Server (see sidebar), and we're still going strong.
Our approach is to split the device-under-test (DUT) from an interface to the test environment that we call Reconfigurable Test Bench (RTB). The RTB allows for test configuration and control. The DUT will change with each rev of the design, but the RTB never changes unless the test environment does. Having a single mass of FPGA's containing a mix of the RTB and DUT designs would have been messy and required unnecessary recompilation of the RTB design, so we separated them out. As a result, we have one set of FPGA's for the DUT and another set for the RTB (Figure 2). The number of DUT FPGA's varies by system size; bigger and smaller systems are available for bigger
Hardware emulation has become a valued component of the hardware/software co-design flow, enabling hardware engineers and software developers to share system and design representations and work together to debug hardware/software interactions.
Use of this tool as a popular EDA solution has evolved over the past 20 years, from the early days of standard FPGA-based emulators to custom ASIC-based models, and then back again to emulators based on standard FPGA's.
CPU and graphics chip engineers were the first to use emulation, because the sheer complexities of their designs crippled traditional event-based hardware description language (HDL) simulators. The tool quickly gained acceptance by the wireless community due to the extensive use of embedded software in its hardware designs. Today, consumer electronics companies widely use hardware emulation for the design of digital TVs, set-top boxes, digital still cameras and camcorders, multifunction printers and other products.
The early version of hardware emulation delivered execution speeds four to five orders of magnitude faster than simulation, making it ideal for accelerating the time required to develop and validate the hardware of ASIC or system-on-chip (SoC) designs. However, it did not meet the minimum speed of execution required for efficient testing of embedded software-namely, 1 MHz. Moreover, cost of ownership hampered emulation's popularity and restricted its adoption to large corporations in limited numbers.
The newer FPGA-based emulators are more reasonably priced and cost-effective, and have shortened the overall verification cycle of complex chip and electronic-systems designs. These emulators have a smaller footprint than prior emulation tools, are fast, efficient and easy to use.
Setup is straightforward and newer emulators consist of fewer FPGA's than older machines. The latest generation of emulation systems can execute billions of verification cycles, as required in embedded designs, in a short period of time. They provide a full view of the design, necessary to debug the hardware. These machines also support transaction-level verification, which is needed for hardware debugging at a high level of abstraction, via monitors, checkers and assertions.
EVE is an FPGA-based emulation trendsetter. On July 14, 2009 it launched the latest incarnation of the ZeBu product line, called ZeBu-Server, a sixth-generation version of its emulator based on the Xilinx Virtex LX330.
Providing design capacity of up to 1 billion ASIC-equivalent gates, ZeBu-Server can be used across the entire development cycle for verifying and debugging a new ASIC or SoC design. Designers can use it to test the integration between hardware and software, and to validate embedded software before silicon availability.
This new emulator improves on previous-generation offerings in terms of capacity, speed, setup time, integration and debugging capabilities. And last but not the least, it is also cost-effective.
— Ludovic Larzul
 Footnote: Logos of current EVE Reference Customers:
The writer would like to acknowledge the direct support of the following individual in the preparation of this EDA Weekly “All About EVE article” -- Dr. Lauro Rizzatti. Other sources reviewed in preparation of the subject article include: The Xcell Journal for Q3 2009 Issue 68 by Xilinx, Inc.; Wikipedia; Hoover's; the EVE website; the Cadence website; “Electronic Design Automation For Integrated Circuits Handbook,” by Lavagno, Martin, and Scheffer; Gary Smith EDA (GSEDA); Yahoo! Finance; and Google Finance. Ongoing support by the team at IBSystems, Inc., including but not limited to Sanjay Gangal, Adam Heller, David Heller, Jon Heller, Nitai
About the Writer of this EDA Weekly:
Since 1996, Dr. Russ Henke has been president of HENKE ASSOCIATES, a San Francisco Bay Area high-tech business & management consulting firm. The number of client companies for HENKE ASSOCIATES now numbers more than forty. During his corporate career, Henke operated sequentially on "both sides" of MCAE-MCAD and EDA, as a software user and as a CAD vendor. He's a veteran corporate executive from Cincinnati Milacron, SDRC, Schlumberger Applicon, Gould Electronics, Automation Technology Products (ATP), and Mentor Graphics Corporation.
Henke is a Fellow of the Society of Manufacturing Engineers (SME) and served on the SME International Board of Directors. Henke was also a board member of SDRC, PDA, ATP, and the MacNeal Schwendler Corporation. He currently serves on the board of Stottler Henke Associates, Inc. Dr. Henke is also a member of the IEEE and a Life Fellow of ASME International.
In April 2006, Dr. Henke received the 2006 Lifetime Achievement Award from the CAD Society, presented by CAD Society president Jeff Rowe at COFES2006 in Scottsdale, AZ. In February 2007, Henke became affiliated with Cyon Research's select group of experts on business and technology issues as a Senior Analyst. This Cyon Research connection aids and supplements Henke's ongoing, independent consulting practice (HENKE ASSOCIATES).
To obtain details of the brand new "2010 Business Planning Tool Kit Promotion" from Henke Associates, please click on the URL below and scroll to the last entry on that page:
Since May 2003 HENKE ASSOCIATES has published a total of eighty-eight (88) independent quarterly Commentaries on MCAD, PLM, EDA and Electronics IP on IBSystems' MCADCafé and EDACafé. Access to the latest of these Commentaries, along with all the EDA Weekly articles posted to date by the writer, may be gained by clicking on this URL:
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-- Russ Henke, EDACafe.com Contributing Editor.
Mr. Ballan also attended Chuo University in Japan as an exchange student. He attended the Stanford University Graduate School of Business-AEA Executive Program. Mr. Ballan is fluent in French, German, English and Japanese.
Two Other EVE Founders:
By the way, the two other founders of EVE in 2000 are Stephane Guerineau, software developer, and David Reynier, application engineer. Both are still at EVE and play key roles in their fields.
OK, OK. I give up. This ain't makin' it! Guess those darn MSEE degrees mean something after all!
Figure 1 - EVE bases its ZeBu emulation system around Xilinx FPGA's.
Figure 2 - ZeBu uses one set of FPGA's for the device under test and another for the Reconfigurable TestBench (RTB).