March 15, 2010
Static Timing Analysis Is Not Staying Static
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The expansion of the market for portable devices, as well as the shrinking geometries of IC have elevated power consumption to great importance. The PrimeTime PX solution expands the PrimeTime timing and signal integrity environment to perform dynamic and leakage power analysis for design geometries at 90-nm and below. Synopsys aims to provide designers with a single, unified analysis environment for timing, signal integrity and power analysis anchored by the PrimeTime static timing solution.
For example, netlist, parasitic and constraint file reads, and tool setup steps are not repeated. As a result, the PrimeTime PX solution delivers up to two times (2x) faster time-to-results (TTR) over separate, standalone solutions.
PrimeTime VX is an SSTA tool. It extends the PrimeTime environment to analyze device and interconnect variations at 65-nm and below using statistical techniques. Variation-aware analysis with the PrimeTime VX solution delivers improved margin control, avoiding the over- and under-design of circuits. Design robustness is improved by pinpointing areas of the chip most susceptible to variations so that designers can reduce this sensitivity and improve the parametric yield of production chips.
PrimeTime VX analyzes systematic or deterministic process variation (die-to-die) as well as random process variation (on-die) in a flexible environment. PrimeTime VX uses a Monte Carlo algorithm that, according to the company, is very efficient and keeps run time to the minimum. By the companies own statements, both Extreme DA and Magma are aiming at replacing PrimeTime in existing deployed installations. They both have stated that the results from their respective products are equal to those of Prime Time. To my knowledge Synopsys has not publicly contested those claims.
Other STA tools
Gary Smith's Wallcharts (available in electronic format at www.gabeoneda.com), provide a database of EDA tools divided by application areas, that are easily searchable by designers. In the segment that lists Timing Analysis tools, Gary lists the following vendors in addition to the two already mentioned: Apache, Cadence, Extreme DA, Incentia Design Ssystems, Mentor, Prolific, and Simucad. To give a better picture of the state of this market segments, it is necessary to briefly describe the products of each of these vendors.
Apache Design Solutions
Although Apache is better known for its power analysis tools, it also offers a timing analysis solution, since power and timing are now closely correlated. At 130nm and above, noise caused by signal crosstalk had the most impact on the chip's performance, whereas at 90nm and below, noise caused by dynamic voltage drop became the main contributor. Now, at 65nm and beyond, both crosstalk and power supply noises are impacting the chip's performance. And since from a device perspective, it is not possible to distinguish whether the noise is caused by crosstalk or dynamic voltage drop, the solution must be able to understand both signal and power supply noise concurrently.
According to the company's description "RedHawk-PSI is a full-chip clock network integrity (jitter) and critical path timing signoff solution for high-performance nanometer designs. It considers the concurrent and interdependent effects of power and signal integrity on clock jitter and critical path timing. Certified by TSMC's Reference Flow, RedHawk-PSI delivers cell-based ease-of-use and performance with true Spice accuracy."
RedHawk-PSI is a dynamic solution, an SSTA, with critical path analysis that is based on real waveform simulation versus a linear approximation. It uses actual Vdd/Vss instance waveforms rather than effective Vdd/Vss approximation of instance supply voltages. The tool represent the effects of dynamic voltage drop and ground bounce on timing by performing dynamic transient analysis of the full-chip power grid and generating dynamic voltage drop waveforms for each instance in the design.
Engineers can obtain standard-cell capacity with a SPICE-accurate simulation of clock tree networks and critical paths, including all the nanometer and high-speed effects, such as crosstalk and dynamic voltage drop. RedHawk-PSI utilizes a true-Spice simulator with proprietary BLSN (big linear, small non-linear) technology to accelerate the solving of networks that have an enormous number of linear elements, and a smaller number of non-linear elements.
Cadence Design Systems
Cadence is one of the very few vendors that offer all the tools required by designers to progress from design implementation to release to a silicon fab. Cadence's timing analysis capabilities are integrated in the company's Encounter family of products. The company states that "with Encounter Timing System, designers benefit from a consistent, integrated, multi-CPU enabled, static timing analysis (STA) environment for place-and-route optimization and signoff verification, leading to faster design closure and better flow convergence." The tool can also be purchased separately, but seems to have been designed to be an integral part of the Encounter Digital Implementation System.
The Encounter Timing System helps designers analyze and debug multimillion-gate designs. Global timing debug pinpoints the root cause of timing and constraint issues at the push of a button. Sophisticated delay calculation ensures accuracy and performance. The tool uses the effective current source model (ECSM) for advanced timing, power, signal integrity (SI), and statistical delay modeling.
This vendor focuses almost exclusively on timing analysis tools. Its product is called GoldTime. The company literature and web site state that "it is capable of running nominal, statistical, Monte Carlo, and SPICE analyses on the full design or any part of the design."
Recognizing the position that Prime Time enjoys in the market, GoldTime is SDC compatible and presents results in the PrimeTime environment. The portion of the tool called GoldTime Analysis performs timing and clock tree analysis. It further calculates the effect of process variation on crosstalk noise and delay. GoldTime Analysis computes variation sensitivities for each cell. Variation sensitivities are the mathematical models for measuring the cell's contribution to yield or clock skew and a key technology driving the statistical optimization engine.
Another component called GoldTime Optimization does post-layout optimization to meet more aggressive constraints and improve design robustness. The company states that "conventional optimization flows based on worst-case corner models tend to push the design to unrealistic performance, causing significant wastage in area and power consumption. GoldTime optimization takes advantage of modeling and analysis capabilities to achieve optimal balance between the performance yield target and power and area requirements."
The product uses a technology called "ThreadWave" that allows the analysis to proceed along a virtual wavefront through the design, and capacity requirements grow sub-linearly with an increase in design size. As only the wavefront consumes system memory, GoldTime with ThreadWave technology can analyze the largest flat designs.
From an execution throughtput point of view, the company claims that on a single CPU workstation, GoldTime demonstrates up to 5X better speed and capacity than current timing analyzers (obviously not including Tekton). On multi-processor workstations, the speed improvement scales with the number of processors.
Incentia Design Ssystems
TimeCraft is Incentia's high-speed, big-capacity, static timing analyzer (STA) for nanometer timing analysis and sign-off. It is the base product of Incentia's complete timing solution offering, including signal integrity (SI) analysis, power analysis (PA), statistical static timing analysis (SSTA), and constraint management (CM).
As with other tools in this market segment, it is compatible with Prime Time. it uses a multi-threaded technology to improve execution time and claims a highly efficient multi-task MM/MC allowing for analyzing more corners in significantly less time while minimizing the use of memory.
The Mentor Graphics timing analysis solution is integrated in its Olympus-SoC IC implementation solution. This flow is highly focused on power analysis, but, of course, includes timing analysis capabilities.
Olympus-SoC provides concurrent optimization for both power and timing, covering all operating modes and process corners through all stages of the flow. It automates multi-supply-voltage design flows with automatic power grid routing for multiple voltage supplies, support for Dynamic Voltage and Frequency Scaling (DVFS) to handle varying supply voltages and clock frequencies, and auto placement and routing of special cells such as level shifters, isolation cells, and MTCMOS switches. Olympus-SoC also provides concurrent multi-Vt optimization, power gating, retention flop synthesis, support for gas station methodology, and power-aware buffering and sizing
To reduce dynamic power, Olympus-SoC provides automatic power-aware clock tree synthesis (CTS) with smart clock gate placement, slew shaping, register clumping and concurrent multi corner multi mode (MCMM) optimization, with the goal of ensuring a balanced clock tree with the minimum number of clock buffers.
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-- Gabe Moretti, EDACafe.com Contributing Editor.