November 30, 2009
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Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

You can translate the success stories from Japanese to English. When I worked for the Japanese company we did that that they essentially said we are using the product and look forward to the next release.

We have seen that. It is always a challenge to get people to write things that endorse you. But we just have to do it.

From a development point of view it sounds like putting one foot in front of the other, leveraging what you have already done.

It is not like we have some new algorithm that we are working on that is going to change the world. One of the things we have learned in this whole process is that the fundamental algorithms down in the heart of the synthesis are not really all that important. It is basically resource allocation. There are a number of academic publications on optimization algorithms. They are all heuristic. There is no single algorithm that will give you an optimal result for every design. Academics think that the whole issue is optimization. We found out that your algorithm can be +/- 20% but it is all the other stuff that really counts. Can you handle memories? What kind of interfaces can you handle?
Can you implement a pipeline? It just goes on and on. These things have nothing to do with the fundamental optimization techniques that are at the heart of the synthesis process. So it is really a matter of trying to put one foot in front of the other.

When we delivered the product to our first customer, Sony, and we got through a project, they came back and said these are all the things we had problems with. If you want us to use this for another project, you need to fix these. We started to fix them. After another project, they said here are some more things. After one and a half to two years, they said now that we have a lot of experience, here is the universe of our designs. You guys are useful in this section. If you do this and this, we can do this section. We started working on that. One and half years later they came back and said “You’ve done all that stuff, now we can do all of our designs.” We have been in
that state with them for about two years now. Other companies have other requirements. Sony has a pretty stylized way of doing designs, pretty standard. You get to Toshiba and Canon or some other people, there are other features or requirements. We just have to work on them one by one. These are not the fundamentals of the synthesis process. They are sort of on the periphery but if you can not do those, they can not use your product.

Anything else to add?

No. I enjoyed speaking with you today.


Since this interview Fotre acquired Arithmatica, Ltd., provider of IP and datapath synthesis based in the United Kingdom, to expand its product offerings and accelerate product development.

Terms of the acquisition were not disclosed.

Forte will continue to develop and market Arithmatica's CellMath(tm) products, including direct support for CellMath Designer(tm) (CMD) and support for CellMath Optimizer(tm) (CMO) through its relationship with Imagination Technologies. It will integrate Arithmatica's patented technology and IP into its Cynthesizer(tm) SystemC

The top articles over the last two weeks as determined by the number of readers were:

DATE 2010 takes off with a new record DATE 2010 proves to be very well positioned in the worldwide electronics industry. While many conferences currently suffer from travel restrictions in many companies and face severe problems in attracting attendees, the total number of submissions for DATE 2010 reached an all-time high of more than 980 submissions.

"This shows the worldwide leadership of DATE as a technical conference and exhibition," said DATE's general chair, Professor Giovanni De Micheli. It is a clear sign that DATE 2010 in Dresden will be the place where all experts will meet and shape the future of our industry. Nobody can afford to miss this event.’

EVE, the leader in hardware/software co-verification, leads the design team acceleration and emulation market, according to the new register transfer level (RTL) Market Trends 2009 Report from Gary Smith EDA.

The report covers calendar year 2008 and forecasts EVE’s market share at 28%, a full three percentage points ahead of its closest competitor. It notes that EVE offers “what many consider to be true design team acceleration and emulation boxes.” Gary Smith EDA defines the design team acceleration and emulation market, as opposed to the verification team acceleration and emulation market, as hardware-based verification solutions that fit on a designer’s desktop and do not impose restrictions on environmental conditions. 

Aptina Picks Silicon Frontline's Post-Layout Verification EDA Software to Eliminate Costly Prototype Builds, Improve Manufacturing Quality Silicon Frontline, an EDA company in the post-layout verification market, announced today that
Aptina, the world's foremost image sensor provider, is using Silicon Frontline's F3D (Fast 3D) software for post-layout verification and for fast 3D extraction to improve Aptina's image sensor design accuracy and manufacturing quality.

Synfora Appoints General Manager for Japan Synfora, Inc., has appointed Mike Arai as general manager of its Japan office. Mr. Arai will be responsible for overseeing all of Synfora’s sales, marketing, support and business development activities in Japan. Mr. Arai was the first employee of Synplicity KK and built the Japanese market for FPGA synthesis as president of Synplicity KK from 2000 to 2008. Prior to Synplicity KK, he was an executive and head of sales at Mentor Graphics Japan, country manager in Japan for Compass Design Automation, and worked for a major Japanese trading
company, where he focused on introducing US technology start-ups to Japan as well as managing distribution for Gateway Design and synthesis products from Synopsys

Satin IP to Participate in Panel on Improving IP Quality vs. Losing Design Productivity at IP-ESC Conference Satin IP Technologies, the company that delivers design quality closure with fast return on investment, will participate in a panel to discuss improving (IP quality without losing design productivity at the IP-Embedded Systems Conference in Grenoble, France on December 1, 2009.

The panel -- entitled “Improving IP Quality vs. Losing Design Productivity – What Are the Tradeoffs?” -- will discuss issues that arise when time-to-market and cost reductions dominate IP design and integration, since instituting design practices for enhanced quality can be seen as overhead by engineers and engineering managers

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-- Jack Horgan, Contributing Editor.

Review Article
  • reviewer November 30, 2009
    Reviewed by 'Mr. reviewer'
    anyone ever bother to proof read your article?

      2 of 4 found this review helpful.
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