May 25, 2009
Popcorn at DAC, Azuro’s CTS, Lotsa news, Cooley’s War
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Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Real Intent also announced
Katsuhiko Sakano has been named General Manager of Japan. Previously, he served as a Senior Sales Manager at SpringSoft, Encirq and NovaFlow. Sakano also has experience at Cadence, Pacific Design, Actel, Xilinx, LSI Logic, and System Design.

Silicon Frontline Technology announced its arrival as a new EDA venture, founded in 2005 and funded in 2007. The company was launched by CEO
Yuri Feinberg and VP of Engineering
Andrei Tcherniaev, who previously co-founded NASSDA (acquired by Synopsys in 2005) and were the original developers of HSIM, the EDA industry's first hierarchical circuit simulator. Feinberg is quoted in the Press Release: "We founded Silicon Frontline with the goal of moving post-layout verification technology to the next level. We want EDA users to experience what hasn't been possible until now – guaranteed accuracy.”

Synopsys announced 2Q09 revenue of $336.8 million, a 3.8% increase over 2Q08. The company projected 3Q09 revenue of $342 million to $350 million.

Synopsys also announced it has acquired the Analog Business Group of
MIPS Technologies for $22 million in cash. The companies say the acquisition “expands Synopsys' DesignWare IP portfolio with a new family of analog IP such as A/D converters, D/A converters, audio codecs and power management. It will also add HDMI TX and RX protocols to Synopsys' existing interface IP solution.”

Tanner EDA announced
Greg Lebsack has been named President. Previously Lebsack served as CEO of ASP Global Services, and held management positions at Sprint. Lebsack is a member of the Board of the Technology Council of Southern California.

Tanner EDA also announced its 20th anniversary, and says the company “has shipped 25,000 licenses of its PC-based electronic design software to 4,000 customers in 67 countries.”


Tools & Technology

Agilent Technologies announced that
TSMC certified Agilent’s GoldenGate RFIC circuit simulator for baseband designs targeting TSMC’s 65LP nanometer and 40LP nanometer processes.

Clemson University announced an agreement under which ANSYS software will be used for engineering simulations at the University’s Computational Center for Mobility Systems, helping “to foster commercial innovation in automotive and other mobility industries, such as aviation/aerospace and energy.”

ANSYS also announced a coupling of the company’s products with those from
Ansoft for multiphysics simulations involving electromagnetic applications. Per the Press Release: “In performing several case studies, ANSYS engineers deployed the electromagnetic effects determined by Ansoft software directly in ANSYS thermal and structural simulation.”

ANSYS also announced the ANSYS 12.0 software suite for “fast product design and validation in a complete, highly usable virtual environment that captures complex and coupled physical phenomena … while reducing the time and money invested in physical prototype development and testing.

Apache Design announced Totem, a new analog design tool the company describes as the “first integrated noise integrity (NI) platform ... Totem is a comprehensive platform that incorporates transistor-level noise injection, parasitics extraction, package modeling, dynamic analysis, and design debug in a single-flow environment … It provides cross-probing of analysis results with industry standard circuit design tools for efficient debugging, fixing, and optimization.”

Apache also announced that the Computers Division of
NEC Corp is using Apache’s RedHawk for SoC design analysis and optimization.

ASSET InterTech announced its ScanWorks platform for embedded instrumentation was used for signal integrity design validation and circuit board test for
Intel’s Xeon processor 5500 series (codenamed Nehalem) and the 5520 chipset.

Azuro announced the first customer tapeout using its Rubix clock concurrent optimization tool.

Azuro also announced that
Newport Media is using Azuro’s PowerCenter tool for clock implementation on all IC designs at 65 nanometers and below.

Berkeley Design Automation announced release 2009_05 of its Analog FastSPICE tool. The new release includes: the Mega-Solver matrix solver, Multi-Core capability for up to 4 cores, enhanced Monte Carlo analysis, 64-bit WaveCrave waveform processing, and new licensing features.

Berkeley Design Automation also announced
Panasonic is using BDA’s Analog FastSPICE platform for verification of mixed-signal ICs.

Berkeley Design Automation also announced that
Alvand Technologies is using BDA's Analog FastSPICE Nano SPICE simulator for analog and mixed-signal IP characterization.

Berkeley Design Automation also announced that
Summit Microelectronics\ has selected the Analog FastSPICE Nano SPICE simulator for block-level characterization of its programmable power management ICs.

Berkeley Design Automation also announced that
SiTime Corp. is using Analog FastSPICE unified verification platform, including the AFS Nano SPICE simulator, for verifying advanced timing circuits.

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To read more news, click here.

-- Peggy Aycinena, Contributing Editor.


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