May 04, 2009
Lynx, For Engineers by Engineers
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Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

If we look at others in the EDA industry, would they claim to have capabilities similar to Lynx?

No. We think this is unique within the EDA industry. I think the only real competition for Lynx is that a company may have developed something similar to it internally. But in terms of someone like Cadence, Magma or Mentor, to the best of my knowledge they don’t have anything like this.

How about reference flows and design kits?

Reference flows are exactly that. They are reference flows. They show an approach to solving a particular problem. They are not meant and they do not purport to be a production environment. First of all, their scripts are not production. They are reference. You have to do a lot of work to set them up to satisfy a production design. They do not have any kind of concept of job automation, ease of flow configuration. Nothing like the Runtime Manager. They do not have any concept of flow configuration or easy debug through Runtime Manager. They certainly do not have anything like the Management Cockpit, realtime insight into the design status and be able to track that across projects as
well as over time for any individual project. I do not think they have anything very tightly tied to foundries. You might argue that some of the stuff that Cadence does in what they call their kits business does some of that. We have not seen that as a significant factor in the market.

As we have discussed, Synopsys has plans for the future. What does a customer do today if they adopt Lynx and want to add say analog design tools to the flow? DO they need a service contract to do that?

It was built fundamentally from the ground up to be modular. You can usually plug in additional modules. It was really designed form day one to be modular because most people have what they would classify as subflows. This is just RTL-to-GSDII. But there are subflows for verification, for ESL, typically for rapid prototyping, for synthesizing a design, for translating a design from a C description to an RZTL description. There are certain DFM and TCad related flows. There are five or six subflows that people use. We recognized that right from the beginning. We are tackling one of these, namely RTL-to-GDSII, right now but very quickly we will be addressing the other subflows.

The top articles over the last two weeks as determined by the number of readers were:

Cadence Techtorial and Workshop: System Level Design and Chip Architecture for Low-Power ICs  This techtorial and workshop provides an in-depth survey of the Cadence system-level design solution for low power, and gives designers an opportunity to “test-drive” these tools on actual designs. For the afternoon labs/workshops Cadence will provide laptop computers, allowing students to work through a tutorial-based manual with assistance from our Field Applications Engineering team. These take place in April at several California sites as well as at Austin, Arden Hills (MN), and
Chelmsford (MA). On May 5th one will be held in Ottawa.

Altium: What makes You So Special? Altium is opening up ta holistic approach to any designer in the world, with a dramatic, low-cost entry to Altium's electronics design solution. Altium Designer is now available at a single, global subscription price of US$195 per month, purchased in 12-month blocks.

Altium Designer's perpetual license price has also been permanently reduced to a single, global price of US$3,995.

Both license options include 12 months’ software assurance which delivers two major product releases per year, along with continuous updates.

Magma Congratulates Winners of MUSIC China "Best Paper" Awards -- Prototyping, Floorplanning and Physical Implementation of Complex Chips Among Popular Topics The top paper award went to Lei Zhang of NVIDIA for his paper titled "Floorplanning a Complicated Partition with the Talus(r) Tcl Interface." The second place award went to Koki Tsurusaki of Renesas Technology for his paper titled "Prototyping a Large-Scale System-on-a-Chip with a Complex Floorplan and Massive Amount of Hard Macros." Third place went to Ding-shan You of the Institute of Computing Technologies, Chinese Academy of
Sciences for his paper titled "The Physical Implementation of a Complex Switch ASIC for a High-Performance Parallel Computing System."

Mentor Graphics TestKompress ATPG Software Wins Test & Measurement World’s Test of Time Award Mentor Graphics announced that its TestKompress ATPG (automatic test pattern generation) product was honored with the 2009 Test of Time award by readers of Test & Measurement World magazine. Mentor Graphics is the first EDA company to receive the award, which recognizes products that continuously deliver state-of-the-art performance for a minimum of five years after introduction.

Apache Design Solutions Introduces Totem, the Industry’s First Power and Noise Integrity Platform for Analog and Mixed-Signal Designs Apache Design Solutions, announced Totem, the industry’s first integrated power and noise integrity platform that addresses the challenges associated with global couplings of power/ground noise, substrate noise, and package / PCB capacitive and inductive noise, for analog, mixed-signal, memory, and high-speed I/O designs. Totem is a comprehensive platform that incorporates transistor-level noise injection, parasitics extraction, package modeling, dynamic
analysis, and design debug in a single-flow environment.

Totem’s key technology is based on the concurrent analysis of noise propagation through the power delivery network, substrate network, and package/PCB parasitics. It accurately analyzes noise coupling effects at every time-point using a single-kernel solver. This advanced technology enables designers to account for all global noise impacts on their designs, a critical challenge for post submicron mixed-signal SoCs.

TSM) today unveiled the first foundry-specific Integrated Sign-Off Flow at its North American Technology Symposium in San Jose, CA. The new flow is available now for 65nm designs.

The Integrated Sign-Off Flow, targeting initially at 65nm process node with planned extensions into other process technology nodes, supports advanced design techniques for low power and design-for-manufacturability (DFM). It includes executable scripts for complete flow automation and EDA tool queuing system support. With validated libraries and IP, qualified EDA tools, full set of proper technology files, and automated installation scripts, Integrated Sign-Off Flow significantly shortens the time it normally takes design team to set up the design environment and flow before starting the design project. The built-in advanced design methodology and proven sign-off scripts further
shortens the design cycle, and improves tape-out quality.

Other EDA News

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-- Jack Horgan, Contributing Editor.

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