March 03, 2003
DVCon Panels Amuse and Amaze
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Peggy Aycinena - Contributing Editor


by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

by Peggy Aycinena

SAN JOSE, California -- Feb. 28, 2003 – Several panels at this year's Design & Verification Conference (DVCon) were definitely worth the price of admission. Cliff Cummings of Sunburst Design and John Cooley of ESNUG moderated back-to-back panels discussing, respectively, “Verilog and Assertions – Do They Mix?” and “Is EDA a Safe Investment?”

Widgets and Wedgies

Cummings started by asking that all cell phones in the room be turned off for the duration of his panel, and then delighted his audience by challenging all in attendance to give “a big old wedgie” to anybody sitting nearby whose cell phone rang nonetheless. (Many noted that Cummings' policy quickly became the principle self-policing tactic referred to throughout the remainder of the conference by DVCon attendees and speakers alike. Amazingly enough however, despite the wedgie threat, cell phones continued to ring hour-after-hour interrupting technical presentation, keynote addresses, and panel discussions – perhaps because Cummings' threat was never actually enforced.)

Cummings tolerated a series of presentations from the speakers on his panel who represented EDA vendors, industry standards organization, and users. Not surprisingly, their comments touched on a range of topics, more or less related to subject at hand, but did not achieve consensus.

Verplex Systems' Harry Foster said assertions-based methodologies are not the sole property of any particular vendor's tool, that bugs are often uncovered prior to verification, and that design and verification will become more closely unified in the future by specifying verification parameters prior to implementation.

Cisco Systems' Sean Smith said that the current divergence between the different verification standards needs to be reconciled and that assertions will ultimately provide the tools for design reuse and standardization – something he said will be in place in 5 to 10 years. He commended the OVL (Open Verilog Library) initiative as being a way by which assertions can be incorporated into common HDLs.

Model Technology's Dennis Brophy, also the Chairman of Accellera, said standardization builds markets and that Mentor Graphics (Model Technology is a Mentor Graphics Company) works to combine and couple the needs of users whether they're working in Perl, JAVA, C++, Vera, Cadence TestBuilder, or 'e.' He said that though the world is becoming much more intertwined, a “SystemVerilog Uber Alles” attitude may not be realistic in the short term when all of the languages he listed are still very much in use.

Verisity Design's Mike McNamera said that incorporating assertion-strategies into the IEEE 1364 Verilog standard was a better way of capturing designers' intent, rather than producing a separate IEEE 1364.2 standard. He said that the industry should start with third-party verification tools and methodologies, and standardize on the survivors who manage to stay afloat in the harsh conditions of the market place. He referenced the failed Esperanto experiments from the mid-20th century, whereby language theorists tried to produce and disseminate a global language to promote world peace. The failure of Esperanto was similar, McNamara said, to the failure of the move to make ADA the
overarching programming language in the world. He added that the current talk of a unified language that spans everything from design to verification ignores the reality of multi-lingual users, and will only end up producing a large, bloated syntax that's too cumbersome to be useful to anyone.

Cadence Design Systems' Erich Marschner said the combinatorial assertions is an idea that's been around for more than 20 years. He said that multi-cycle assertions should be HDL independent and that the language semantics should be more abstract and precise. He said verification constructs should be put outside of the HDLs to prevent importing “baggage” into the design process and that multi-cycle assertions may prove to be the next-generation design language.

Finally, Synopsys' Stephen Meier said that what is needed is a group of tight, well-defined assertion capabilities within Verilog. He noted that SystemVerilog V3.1 will be available by DAC 2003 and that the hierarchical, assertion-based methodologies support the concepts of design for verification. He added that IP vendors should work to supply assertions, along with verification language experts.

The speakers ran long and Cummings was hard-pressed to steal a few minutes for Q&A after the presentations. A question from the floor asked if there should be different classes of assertions between design and verification engineers.

Erich Marschner responded, “The verification engineer wants to look at a design as a black box. He doesn't want to look inside. For his sake, the assertions should be about the periphery and interface. On the other hand, the design engineer wants to capture what he knows and is thinking about the design. His assertions should have the ability to express the non-deterministic nature of the design.”

Many felt that substantive debate had just begun, but Cummings had to relinquish the podium and the panel chairs to John Cooley and his group waiting in the wings.

Lookin' fly, in suit and tie

A dapper John Cooley then took the podium and proceeded to oversee a chaotic hour, which was less panel discussion and more fast-paced improvisational theater featuring an ensemble cast. No one in the audience seemed to mind, apparently satisfied that an hour long on entertainment, but short on solid fact, was an appropriate segue to the Happy Hour that followed next. Not surprisingly, few panel member came even close to answering the question at hand – “Is EDA a Safe Investment?”

Cooley started by recounting the reasons that none of the Big Three EDA vendors had agreed to appear on the panel, and then asked Earch Desai to open the discussion as Cooley credited Desai for being the principle reason that Mentor, then Synopsys, then Cadence declined Cooley's invitation to participate.

American Technology Research's Erach Desai declined to respond to Cooley's comments, but instead contrasted bullish versus bearish views of the publicly traded companies within EDA. He said investors won't make much money in EDA unless they choose either Cadence or Synopsys. Investing in smaller EDA companies, he said, is only a “hope-and-pray” strategy. However, he said there are certain technology growth drivers in the industry and that the critical tools that EDA vendors provide can provide a legitimate investment vehicle.

Speaking bearishly, Desai said that since the 2000/2001 timeframe, the EDA “pie” has not been growing and that there continues to be “confusion” with regards to the appropriate business model within EDA companies. He added that consolidation will continue in the industry, while some portion of the EDA business model will still rely on companies suing each other.

Cooley asked Desai which small companies are actually providing innovation in EDA. Desai said, “Some companies need to die.” Cooley countered, “Which ones?” Desai declined to answer.

Following this exchange, the panel devolved into a free-for-all, with speakers throwing over ideas, market messaging, and pointed barbs directed at the larger EDA companies.

Lanza TechVentures' Lucio Lanza said EDA has always been characterized by fragmentation and consolidation, and that innovation comes from fragmentation – but he has “nothing against EDA.”

Magma Design Automation's Rajeev Madhavan (who won the award for most visuals and overt company messaging) added constructive commentary when he said, “Nobody can go it alone in EDA. The small companies need to come together and put their egos aside.” Each of Madhavan's comments during the hour required a trip to the overhead projector.

Monterey Design Systems' Jacques Benkoski said, “The situation in EDA is one of constant change and innovation.” He described a 3-step process where 1) people don't understand a problem, 2) they analyze a tool that might ease the pain of a problem, and 3) they construct the tool. However, he said, the problem is never viewed as a “real problem” until the technology to solve the problem becomes part of a bigger company. So companies are advised, he said, to “stay small and then get acquired.”

Erach Desai responded, “I'm actually not that far out of agreement with Jacques. I feel that right now, we're in a node where consolidation is imperative for EDA companies to survive. We go through waves of point tools versus a consolidated flow, and we're extremely in need of a consolidation phase right now.”

Verisity Design's Moshe Gavrielov jumped in and said, “Every industry is driven by the customer base. The fact that the EDA 'pie' isn't growing needs to be kept in context. The industry's still making a respectable showing and there's a great opportunity there despite the 'minor issues' that people are talking about here.”

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-- Peggy Aycinena, EDACafe.com Contributing Editor.




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