February 02, 2009
You Can Never Have Too Much Performance
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor


by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


Is the parallelization technology for a single computer with multiple cores, for multiple computers, for multiple computers each with multiple cores, or all of the above?

We are taking a phased approach. We started off with Turbo technology and now we have APS. The first phase of APS addresses the ability to run and improve performance on a single machine with multiple cores. That is an easier problem to solve right away. We looked at that because computers with multiple cores are more cost effective. Now, moving forward, we are also looking at what people in the industry call distributed performance, distributed processor performance where we are going to introduce technology that enables our customers to run their simulation on multiple computers with multiple cores. That is a little bit more of a difficult problem to solve. There is latency between
the machines. You want to take that into account and make sure that the added performance is significant enough compared to the latency between the machines, the handshaking that goes on among the machines. The APS product we introduced in December is for a single machine with multiple cores. Currently, it runs up to 8 cores. Sixteen cores was something we were targeting but because if some hardware limitations, sixteen cores are not fine tuned as of yet. We are now delivering only up to eight cores. The next phase is going to be distributed processing.


Do you have a timeframe on that?

That’s something we are working on. We have not set a particular timeframe yet, but we are looking at 2009.


As you increase the number of cores, does the performance go up linearly?

In theory we would like it to be linear.


The release of 7.1 is where we introduced ASP. We launched it in December and released it on January 14th. Spectre is the SPICE solution for analog blocks and analog IPO. All this is under the umbrella of AMS Design Analog and Mixed Signal. All these technologies share the same infrastructure and the same device models and serve the RF, Mixed Signal and Analog markets.


The phased approach of introducing performance improvements started with Spectre Turbo for Analog Design, then Spectre Turbo for RF Design and now APS. APS delivers parallelization, basically multithreaded. It is scalable. So, the question you asked earlier was “Is the performance linear with the number of cores?” In theory we expect it to be linear but there is always some latency involved with multicore. Our customers have seen significant performance improvement versus single core and linearity depending upon the design and the machine they are using. It runs anywhere from three to five times across the cores when executing on 2, 4 and 8 cores. Just to give you a
perspective in the kind of performance we are seeing; for an ADC (analog to digital converter) at 65 nm, customers have seen a factor of twenty-nine speed up. I should say that we have seen internally on a customer design this type of performance compared to Virtuoso Spectre. We just put out a press release where customers saw a significant performance improvement using this technology. In fact in one case, they were able to catch errors that would have required a silicon respin.


APS serves customer for post layout verification. There is no change in use model, the same accuracy. Now they are able to these large designs with large amounts of Rs and Cs and simulate them.




Multithreading. You may have heard the term out in the industry in reference to many types of simulation capabilities. Full parallelization is the key. What this means is that it is not just parallelizing the device analysis which is a significant portion of the circuit. It is also parallelizing the solution of the circuit. That is what we refer to as complete multithreading which is parallelizing about 90% of the simulation operation. In particular as design get larger, the matrix of the circuit gets larger. The need to parallelize the portion of simulation is huge with respect to improving performance.

From your standpoint working in this industry, what are the key challenges that you hear for custom simulation?


For any type of simulation, it is accuracy, time and cost and as you have said the ability to fit into an existing design flow with minimum disruption.

Exactly! Without disruption! Adoption barriers are very important. Particularly, if they are working on one version of their design flow, they do not want the disruption that changing to a new tool or new solution will likely entail. So being able to take a solution and being able to plug it in is very important. That is one of the reasons we have made sure that for Spectre Turbo, Analog and RF we have maintained the same use model for the customers. All that is involved is really just invoking that tool but with the same settings, same netlist, same device models and so forth.


Is APS targeted more at Analog, RF or Mixed Signal?

It is targeted at analog and RF functions. When we are talking about what kind of designs, it is analog and RF blocks, IP and subsystems because one of the key benefits is the capacity if being able to simulate large block designs that customers were not able to simulate before within a certain timeframe. In terms of the types of designs, it ranges anywhere from PLL (Phased Lock Loops), data converters, memory IP, power managing circuits, high speed IOs, transceivers.


Is the license for the product node locked or floating?

We should not be talking about node lock or floating. It is really how the customers access this technology. The new product is within our Multi-mode Simulation (MMSIM) solution with token licensing. Customers that have the tokens are able to check out the technology and run it. A token based scheme.


Is there a price point for this product?

We have a price list available to our customers.


Is it available to me and my readers?

No. It is a two dimensional price based upon device count as well as the number of cores.


Can you give me a price range?

We can not give out any dollar figures. It is available to customers through our account teams.


Who does Cadence see as its competition in this arena?

Good question. There are a lot of big companies out there that tout parallelization. Most of these are partial rather than complete parallelization. Then there are some firms that are emerging that also tout parallelization. There are a whole set of EDA companies that are out there.


Do you have a sense of what market share Cadence has in this area?

In analog, in custom simulation, in …? The APS serves the analog simulation market.


In that market segment then.

The market breaks down in two analog simulation aspect and characterization. We have over 45% market share.


Does that make you number one?

Yes!


Who is number two and three?

I think Synopsys is next followed by Mentor Graphics.


Do you have any sense for the dollar figure for this market?

I can not comment at this time.


Any closing remarks for my readership?

Cadence is committed to the SPICE simulation in general mixed signal SPCIE simulation. 2008 was the first phase with Turbo and APS. We are continuing to invest significantly in this area not just in the SPICE simulation but in mixed signal verification. We will be rolling out some key pieces of technology to enable customers to their deign and verification


The top articles over the last two weeks as determined by the number of readers were:


Synfora Achieves 250 Percent Revenue Growth, Expanded Customer Base in 2008 Synfora, Inc. announced that it had an increase in revenues of 250 percent in calendar year 2008, and that it significantly added to its customer base. Synfora said that the growth was fueled by the continuing worldwide acceptance and adoption of its PICO Extreme™ design tools. Synfora announced PICO Extreme™, a breakthrough algorithmic synthesis technology that enables the implementation of dramatically larger and more complex sub-systems
using an innovative TCAB (tightly coupled accelerator blocks) approach. PICO Extreme allows familiar design styles, reduces runtime and achieves unprecedented quality of results, including reduced power. Synfora also launched its PICO Extreme FPGA product, signed its first FPGA customer and joined the Xilinx ESL initiative, marking its entry into the fast-growing FPGA market. PICO Extreme FPGA is optimized for Xilinx high-performance 65 nm Virtex™-5 and low-cost Spartan™-devices.


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