[ Back ]   [ More News ]   [ Home ]
December 01, 2008
Envis - Low Power
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


On October 28th Envis Corporation announced the hiring if industry veteran AJ Sen as President and CEO. Envis, formerly Envision Technology, is an early stage startup company that offers products and services that help automatically reduce power consumption in SoC designs. I recently had an opportunity talk with AJ Sen ahd Holly Stump, VP Marketing, in a conference call.

Would you give us a brief biology? I mean a brief biography.

I could talk about biology. I will go through my background. First, I graduated as an engineer in the late 80s. My first job was as a design engineer at Zilog. I did mixed signal designs for chips that went into TVs and other consumer products. That company had an IPO. I got bitten by the Silicon Valley startup bug. I decided after that point that “Well hey, everybody else is doing it.” It has been my passion. Let me go start a company. That was what I was thinking. I did not do that immediately. I went on from engineering into marketing at a wireless company for a couple of years. I at least saw the business side of the Silicon Valley and then went on to start a company in the semiconductor space called PulseCore Inc. PulseCore was venture backed. We supplied chips for timing and EMI reduction, mixed signal chips. The company ultimately got acquired by Alliant Semiconductor. After that I decided to do something quite a bit larger in scope. We were in the middle of the tech bubble. It seemed to be the right time. I started eSilicon. I wrote the business plan at my kitchen table. My wife named the company. Then I started to put the team together to make the dream a reality. eSilicon is doing reasonably well, great revenues,; graphs are going upward and to the right. After eSilicon, I decided to start an analog service and IP company. This time I did not raise
venture capital but bootstrapped it. I was the main investor there. That was Astro Services. I ran that for about four years. We were selling high speed SERDES IP. Then we sold it to a group of foreign folks, who wanted to extend their IP portfolio. After that I spent a couple of years as CEO of mSilica, an early stage company that is doing well now, making power management chips to drive LEDs in flat panel displays, for example big screen TVs. After that, I came to Envis.

The reason I joined Envis was first of all the space that it is in. I believe that the biggest pain point going forward is power when it comes not just to semiconductors but also data centers, the energy consumption in buildings. Power is the center point and the number one pain point. The second reason for joining Envis is the quality of the team. There is a stellar CTO here, Hamid Savoj. He was one of the founders at Magma and took it public. Of course there is Holly (Stump) in Marketing. The engineering team is just the best and brightest that I have come across. That’s sort of a long version of my background.

You have been involved in several successful startups. What do you believe are the key ingredients for a successful startup?

Actually, at the end of the day there are two that I value highly. First, you have to be in a big market. You can be the best at what you do in a tiny, niche market and your success is severely constrained, the growth is severely constrained. You need to be in the presence of a large or a small but rapidly growing market. The number two ingredient is the team. By team, I mean something specific. It is the mental horsepower of the team. In the Silicon Valley everybody works putting in 10 to 12 hours day. Everybody is ambitious. What separates one startup from three, four or ten others in that competitive space is the raw mental horsepower of the core team. By core team I mean the first
twenty guys or gals in the company. So for me it is the team and the market.

What were you doing just before you joined Envis?

I was CEO at mSilica.

Editor: Prior to joining Envis in June 2008, Holly Stump was vice president of marketing at Sequence Design. Stump cofounded or was on the executive staff at several successful EDA startups which have been acquired by industry leaders, including Logic Modeling Systems (now Synopsys), Precedence (now Mentor Graphics), and Interconnectix (Mentor Graphics). She has also held senior marketing and business development positions at Cadence Design Systems, IKOS, and Valid Logic Systems

What is the background on Envis? Who started Envis, when and why?

That predates my arrival here by two to two and a half years. I believe Envis was started in the middle of 2006 by a founder who is no longer with the company. The goal right from the get-go was to manage and reduce power on computer chips.

We have stayed true to that goal. Shortly after Envis was founded, Hamid (Savoj) came on board and took the role of leading the technical team. We have just now started delivering product to a small set of friendly customers. The company has raised just about $6 million in one round. That’s where we stand right now.

Does Envis have any plans to raise more money in the near term?

These plans are always there. We may look at that next year. Right now what we are focused on is building our sales pipeline and getting very intimate with a small number of world class customers. We are well on our way to doing that.

What is the size of Envis now?

It is small by design. With contractors and employees, it is just shy of twenty people. I just want to make a point here. I am very happy about the fact that our burn rate is small and that we have our costs under control. This is definitely not the time to be a startup with a million dollar burn rate per year, looking for revenue or having a small amount of revenue traction because the sales mood and more so the investment mood over the next twelve to eighteen months is going to be quite challenging.

You mentioned working closely with some companies. Are you shipping product for revenue now?

We are just starting to ship product for revenue. We have not actually done that yet. The early engagements are structured around more of a design service flavor than actual traditional EDA, IP and software sales. We felt that entering the market with a design services offering actually helps us tremendously in fine tuning our feature set. And when we do roll out our products, production worthy versions of our products next year, we will have everything finely tuned just right.

As you mention power is a pain point in many different areas. Have you got some focus in terms of the friendly companies you are working with?

Right! These companies typically ship very large volumes of SoCs that have upwards of three or four million gates all the way to ten to fifteen million gates. They are quite broad in their applications. Frankly, everything from network processors, things that go into data centers all the way to wireless and consumer products. We are very horizontal when it comes to applications of the chips but they all have the common problem that they are struggling to meet their power budget. They do not want to put custom tools on their packages, heat slugs or go to different packages altogether. Just meeting their power budget is a challenge.

As I see on the Envis website, there are two products, namely Chill and Kelvin. Would you tell us is a little about each of them?

Right, now we have two products, although we have already started a couple of roadmap items that we can talk about later.

Chill is essentially a very advanced version of clock gating product. We do the traditional clock gating that designers have come to use over the years, added very clever new algorithms to take it beyond just routine clock gating. When we benchmark Chill against a couple of the other folks who provide clock gating solutions, we are getting twenty percent improvement.

Kelvin is what we call an APPG, automatic power pattern generator. What we found is that we are getting quite a bit of traction with Kelvin. Designers do not usually prioritize pattern generation to flex and measure the power profile until it is almost too late. With Kelvin we give them a chance upfront to really think about how your are going to exercise the design, to unmask all the different power profiles that a chip can have.

Would you explain a little bit more about the approach that Chill uses?

I can go through just basically what is under the hood in the Chill product. First, we have algorithms that are combinational to detect activity and then remove flip flops without, of course, changing the design. We have bucketed them into a number of different combinational methods. Generally that is the most straightforward and accepted approach to clock gating. We have also what we internally are calling sequential algorithms. Again flip flops are removed by doing analysis of sequential paths. That is also something that competitors do. As a byproduct we also have logic optimization built-in. We remove equivalent flip flops. Each of these contribute anywhere from two to three
percent all the way to twenty percent. You have to add them all up in terms of power savings. All the techniques I just described address active power. What was have on our roadmap are some very interesting approaches to static power, in other words to the leakage problem. The reason that is important is that even the dirt cheap mass produced ICs that go into consumer products used to be .18 microns. They went to .13 microns. Even those are starting to migrate to 65nm. At 65nm, when your average design shop in Taiwan is primarily moving to 65nm, leakage becomes by far the biggest problem in managing power. We have some clever approaches in our roadmap to address that.

What is the price point of the products?

The list price is competitive but at the same time heavily valued-based. We believe that we bring tremendous value to this market above and beyond what others are offering. We are hesitant to disclose price points right now. Give us a little more time. Early next year we would be glad to do that.

I thought that I saw some prices in a press release.

Those prices have been revised.

Where do the two products fit in the design flow?

They are net list products. They take a netlist in and output a netlist. Ideally, they are used in the front end, typically after synthesis. They are not used at the RTL level and they are not backend products.

Holly: Because Chill, in particular, runs at the gate level, it is usually run after synthesis. Front end designers are interested to get early visibility to the power before they do the handoff. Having said that, we see apps from certain implementation groups, like design services companies that are also finding it useful, because they can get the gate level handoff and they can still do things to control power as part of their charter. It depends on how the company does the handoff but we have seen both front and back end.

Kelvin is run before Chill to obtain a baseline power analysis. Chill is then run to reduce static and dynamic power. Kelvin is then run again after Chill to perform power analysis and obtain the estimated power saving.' width=

Kelvin is run before Chill to obtain a baseline power analysis. Chill is then run to reduce static and dynamic power. Kelvin is then run again after Chill to perform power analysis and obtain the estimated power saving.

How do you test your product? How do you know that your products reduces power by whatever percentage?

That’s the big unknown in this field. There are a number of power estimation techniques that designers use. Ultimately, you have to characterize what other products in the same space have in terms of power dissipation and bench mark against them. It is difficult to measure absolute power reduction.

Holly: I may not understand your question correctly but when we measure power reduction we use third party commercial tools that have been out there forever. Power measurement at the gate level is kind of a commodity. Right? You can use anyone’s gate level power estimation before we run Chill and after we run Chill. You can run it at the front end. You can take it all the way through layout and run that power estimation again. We are seeing very good correlation between what we say we can reduce power at the front end with commercial power measurement tools and what we are actually doing post place and route.

When you approach a prospect, how do they convince themselves that your software does what you claim it does? Do they give a problem chip?

We are in exactly those kinds of engagements now. I will describe a couple of generic engagements. One of them is a well known firm that has a huge portfolio of IP. They feel that have neglected power. We are engaged with them to go through their entire IP portfolio and see what kinds of power reduction we can offer. That is more of a design services offering from Envis than anything else. We get reimbursed based on success which is the real and fairest way to engage. In terms of turn around time to finish, it can be as low as a week. I would say it typically ends up being a two week effort. So at the start of two weeks, we understand what IP or what block or what SoC we need to focus
on. At the end of two weeks, we deliver back to the customer that same block that passes all formal verification that show anywhere from twenty to sixty percent reduction in power. That’s more of a front end approach as far as the customer is concerned.

There is a second kind of engagement that we are seeing. That is where a customer is under the gun to tapeout a chip and they have tried several approaches. They have various EDA tools. They just can not meet their power budget. As a last ditch effort, someone calls us and asks if we can help. Those are challenging, because we end up overnight being under the gun for the tapeout like the customer. I have taped out dozens of chips and it is not a pretty place to be. But that is okay. We have to deliver results. The tapeout is put on hold. There is a lot of pressure on us to do it. In more cases than not, we are able to deliver. So those are the two flavors of engagement right now.

Given the size of the company and the design services approaches, does Envis have a geographic or industry focus?

We do not have an industry focus. As I have said, we are very horizontal in terms of what chips our techniques can do. But being small we are focused on the Bay Area. There are a number of great semiconductor companies in this area. They all have very hard to meet power requirements. As a next step, we have started to look at Japan and just started to engage with a small number of large Japanese IDMs or ASIC houses, who, by the way, also have factories here. But primarily, it is the Bay Area. We do have a couple in southern California.

Are there any specific competitors that Envis runs up against? Do prospects have their own internal tools?

Again, for the design services model, we have not really seen or bumped up in the field against anyone who is developing a very high valued-add tool and offering design services. On the power services front, we are not really seeing anybody. On the tools front, sure, Synopsys has got PowerCompiler and on the front end you have Calypto with PowerPro. I would say those are the two flavors we see most often. We are confident that e can out perform both.

As the new CEO at Envis, what do you see as yur major challenge, what is your area of focus?

Growing sales! That is what it is all about. I’ve been around the Valley long enough to now that the best products with the best teams and with the biggest markets, do not mean anything until revenue comes pouring in. So, “sales” is it. That said, I am very optimistic about the roadmap we have in place. The company has put a lot of thought into it. There is tremendous customer validation. We’ve started with clock gating as the low hanging fruit. We have some pretty unique adaptive voltage scaling technology that we would like to roll out. I can not commit to the timeframe. But early patents are being filed. There are a couple of additional roadmap items.

Is the current economic climate more of an obstacle or an opportunity for Envis?

It is a littler bit of both. I will go into why. It is clearly an obstacle. When times are good, people are writing checks left and right. Ultimately, everyone’s mood in the morning coming to work is better. We would all like it to be like in the late nineties again. But there is an upside, a silver lining of being in the mood we are in. Number one, we can hire the best in class because several of them are not currently employed. For example, on the apps engineering front, we are looking to expand. We now a handful of people that got laid off who should not have been laid off, who are A one players. So hiring is not nearly as much of a problem right now as it could be. The second
thing, being a small and nimble company with very low burn rate, we can hunker down and engage very selectively with a handful of top tier, the top twenty IDMs in the world and take it slowly. We have the luxury to do that. In boom times we would be following a different growth profile. So that is a couple of reasons why it is not all bad, when the market takes as turn as it has right now.

Any significance to the name Envis?

I believe the origin of the name originally was Envision Technology. It turned out that the name as not fully available from a trademark point of view. So it got abbreviated to Envis.

I am out of questions. Do you have anything to add?

You have tremendous visibility into this ecosystem. What is on the top of your mind?

The economy! My 401K!

Yeah. I came to this country when I was eighteen years old. That was about twenty-five years ago or so. We live in the best company n the world with the strongest economy. My two cents worth is, as I tell my wife, that we have not sold anything in our 401K and it will come back. It has to. That’s what I believe.

Well, let’s hope so for all of our sakes.

The top articles over the last two weeks as determined by the number of readers were:

Mentor Graphics Reports Fiscal Third Quarter Results Mentor announced revenues for fiscal third quarter ending October 31st, 2008 of $184.9 million, a GAAP loss of $.85 per share, and a non-GAAP loss of $.04 per share. The GAAP loss is primarily driven by a $.55 per share tax provision that is abnormally high as it includes recapture of tax benefits previously claimed in prior quarters as well as the continuing effect of tax expense in non-US jurisdictions.

Cadence Announces Appointments of R&D and Worldwide Field Operations Leaders Chi-Ping Hsu, 53, was named senior vice president of research and development for the Implementation Products Group. Hsu has previously served as chief strategist of products and technologies and corporate vice president and general manager of both synthesis solutions and digital IC implementation. Nimish Modi, 46, was named senior vice president of research and development for the Front End Group. Prior to joining Cadence in 2006, Modi spent 18 years at Intel Corporation, where he was most recently a vice
president in the Enterprise Platforms Group. Tom Cooley, 46, was named senior vice president of Worldwide Field Operations. As previously announced, Cooley is responsible for worldwide sales, product marketing, and technical field operations. Cooley is an EDA industry veteran with over 23 years of experience in sales and marketing

DeepChip ESNUG article: Why we dumped PrimeTime (and skipped Cadence ETS) for GoldTime

Analog Design Solution Company Solido Signs Martin Harding to Lead Worldwide Sales and Marketing Efforts  Solido Design Automation announced that Martin Harding, a highly experienced semiconductor and EDA sales and marketing executive, has joined the company in the newly created position of Vice President, Worldwide Sales and Marketing. Based in San Jose, Calif., and reporting directly to CEO Amit Gupta. Mr. Harding has established worldwide sales and marketing forces, and been instrumental in growing company sales and customer bases, at numerous successful start-ups. He was most recently
President and CEO of Tenison Design Automation

Nascentric Announces Second Generation, GPU Accelerated Spice Simulator, OmegaSim™ GX  Nascentric, Inc unveiled the second generation OmegaSim™ GX today. Now the NVIDIA Tesla GPU Computing Processor is leveraged to speed up both the simulation solver and transistor evaluations in OmegaSim GX. In addition, OmegaSim GX now supports single-CPU/multi-GPU configurations using the Tesla GPU Computing Processor. North American pricing for OmegaSim GX software is $25,000 per year or $2,500 per month. The minimum subscription commitment is 10 months. Hardware is separately priced and must be
purchased from NVIDIA, its partners or resellers.

Other EDA News

Dassault Systemes Launches V6R2009x

JEDA Launches The First Commercial TLM2.0 Compliance Checker

AWR and Rohde & Schwarz Japan Enter into Sales Partnership

HP Reports Fourth Quarter 2008 Results

Si2’s Low Power Coalition Releases Power-Aware Design Flow and Power Reduction Documents

Cadence Receives Notice From NASDAQ Due to Delay in Filing Its Quarterly Report on Form 10-Q

Creative Chips Adopts Synopsys' Galaxy Custom Designer Mixed-Signal Implementation Solution

Fluid Flow Simulation Helps Overcome Tough Telecom Thermal Design Challenge

Tanner EDA to Present on Layout Design and Verification for Analog and Mixed-Signal and MEMS Design at MAP2008

Cadence Announces Appointments of R&D and Worldwide Field Operations Leaders

TRADE NEWS: Agilent Technologies’ Electronic System-Level EDA Platform Earns eg3.com’s Editors’ Choice Award

Analog Design Solution Company Solido Signs Martin Harding to Lead Worldwide Sales and Marketing Efforts

DeepChip ESNUG article: Why we dumped PrimeTime (and skipped Cadence ETS) for GoldTime

Synopsys Unveils IP OEM Partner Program with Arrow Electronics, Global Unichip and Open-Silicon

SCDSource Article: Improving statistical design for analog/custom circuits

Agilent Technologies Announces Industry’s First Licensing Model Dedicated to Advanced Verification for RFICs

Embedded Market Forecasters Publish In-Depth Analysis of Model-Driven Development as a Best Practice for Safety-Critical Application Development

Mentor Graphics Reports Fiscal Third Quarter Results

Synopsys Unveils Breakthrough Modeling Technology to Address Library Data Size Explosion at 45-nm and Below

OCP-IP Releases New OCP Checker as Part of CoreCreator™ II Tool

Nascentric Announces Second Generation, GPU Accelerated Spice Simulator, OmegaSim™ GX

Accelerated Designs, Inc. Announces Integrated Interface to Digi-Key Part Data

Asahi Kasei EMD Selects Berkeley Design Automation Analog FastSPICE™ for Precision Mixed-Signal Simulation

Tensilica Presents "How to Avoid the Traps and Pitfalls of SOC Design"

Bluespec Announces SCE-MI: Enabling Faster IP Verification Webinar

Carbon and Tensilica Partner for Pre-Silicon Firmware Development

HP Announces Preliminary Fourth Quarter Results

Blue Pearl Software’s Version 4.0 of Cobalt Timing Constraint Generation™ Speeds-Up Timing Closure

Genesys Logic Selects nSys for SuperSpeed USB Verification

Aldec Releases Unified 64-bit Multi-Threaded HDL Design Environment

Other Embedded, IP & SoC News

BASF and OSRAM Set New Standards for OLEDs

Toshiba to Launch 16GB microSDHC

Linear Technology and Power-One Announce Digital Power Technology License

Lattice Enhances SPI4.2 Solutions

ASMedia Licenses Range of MIPS® Cores for Multimedia SoC Development

Open-Plug powers the new J132 mobile phone from Sony Ericsson

Imagination Technologies Licenses High-performance Graphics Processor Core to a Major International Consumer Electronics Company

Digital Blocks Extends the DB9000 TFT LCD Controller IP Core Family with the availability of the DB9000AXI for the AMBA 3.0 Interconnect

WiNetworks Receives First FCC Authorization for Mobile WiMAX(TM) 802.16e Base Station for 3.65 GHz Networks

Elan Digital Simplifies ZigBee(R) PCMCIA Interface

TriAccess Technologies Announces a New On-Chip Linearization RFIC Amplifier Solution Designed for CATV Edge QAM and Other Applications

Avago Technologies Simplifies GPS Designs With First Complete GPS RF Front End Module With FBAR Filters

Advanced ID-Card Controller from STMicroelectronics Enhances Secure e-Government Services

Pulse Introduces Dual-phase Coupled Inductor for Notebook Computers

UMC Advances Its High-k/Metal-Gate Process Solution

Avago Technologies Introduces One of the Industry’s First Optically Isolated Sigma-Delta Modulators for Use in Industrial Motor Apps

Federal Trade Commission Files Petition for Certiorari in the Supreme Court in Rambus Case

Samsung Now Producing 256GB Solid State Drive

Micrel and Zilog Announce Technology Partnership

Imagination announces latest POWERVR VXE video encoder IP cores

POWERVR SGX520, the world's smallest OpenGL ES 2.0 core achieves Khronos conformance

Ultra-low power 16-bit microcontroller core consumes less than 40 μA per MIPS.

Sundance and Dillon Marry Fastest FFT with Fastest Virtex-5 LXT FPGA

MagnaChip Offers Industry Leading 0.18um and 0.35um aBCD (Advanced Bipolar CMOS-DMOS) Process Technology

Growthink Raising $6 Million Series B Round for XCOM Wireless

Diodes Incorporated Introduces Smart Motor Controller That Provides All-in-One Solution

TI 1.5-A linear battery chargers maximize AC adapter and USB input power

Lightstorm Networks Introduces Family of Low Cost and Low Power Carrier Ethernet Switches Designed for Access Market

Intel, Micron Move into Mass Production with 34nm NAND Flash

Cypress Webcast on December 3 Shows How to Leverage CyFi™ Low-Power RF to Overcome Embedded Wireless Challenges

SIA Forecast: Semiconductor Sales Slowing

Europe VC Investment Dips 5% to Euro 1.18 Billion in 3rd Quarter as Deal Activity Nears Historic Low

Xilinx Releases Industry's First Complete Digital Front-End Design to Accelerate Development of 3GPP LTE Radios for Wireless Base Stations

Sundance and Dillon Engineering Merge Signal Processing Expertise and FFT IP to Deliver Benchmark Performance for Embedded Defense, Industrial, Geophysical & Medical Systems

TI introduces single-supply, auto-zero sensor amplifier with programmable gain and offset

STMicroelectronics Collaborates with Microsystems Technology Laboratories at MIT on Ultra-Low-Power Microcontroller Devices

Samsung Now Producing 256GB Solid State Drive

VirtualLogix Supports All ARM Multicore Platforms

Coreworks introduces SideWorks™, a high-performance, small footprint and ultra low power licensable Digital Signal Processing (DSP) Core

Forty CAST IP Cores Validated for Mentor Graphic’s Precision FPGA Synthesis Tool

Microtronix updates Multi-port SDRAM Memory Controller IP Cores to support Stratix III and Arria GX FPGA devices.

Faraday Technology and Fresco Logic Partner to Validate SuperSpeed USB PHY (USB 3.0) with SuperSpeed Digital xHCI Host and Device Controller

VinChip announces USB 3.0 Verification IP for Super Speed USB Devices

Aviza Technology Announces Fiscal Year 2008 Fourth Quarter and Year-End Financial Results

MOSAID Reports Results for Second Quarter Fiscal 2009 and Dividend

Xilinx Offers First 5Gbps FPGA-Based Solution Compliant With PCI Express Version 2.0

Teridian Semiconductor Licenses ColdFire® Architecture from IPextreme®

Pixelplus Announces Preliminary Approval of Settlement of Shareholder Class Action Lawsuit

IDT and Digi-Key Enter Distribution Agreement

ARM Unveils the ARM IP Portfolio Program - A New Model for ARM IP

Sandbridge Rolls Out 65nm Dynamically Reprogrammable, 4G Capable Baseband Platform for Smartphones

Xilinx and Eutecus Demonstrate Programmable Embedded Video Analytics Platform at Electronica 2008

NXP Semiconductors signs agreement with Imagination for graphics technology

Ralink Leverages MIPS32® Processors in 802.11n Access Point/Router SoCs for Broadband, VoIP, Gaming and Entertainment Applications

SiRF signs licence agreement for Imagination Technologies' multimedia IP

ON Semiconductor’s New Highly-Integrated Overvoltage Protection IC Reduces Board Space in Portable Devices by Up to 40 Percent

Ambric Announces Sale of Company and Assets

Tech-X Corporation Announces a Library of Mathematical Kernels of Vector Operations for NVIDIA GPUs

Merrimac Reports Third Quarter 2008 Results

You can find the full EDACafe event calendar here.

To read more news, click here.

-- Jack Horgan, EDACafe.com Contributing Editor.