November 03, 2008
Computational Lithography
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Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Where does the competition stand versus Mentor’s current and future products?

I don’t really know. I have not heard about the competitive products in this realm. We believe that we have an early jump by virtue of our collaboration with IBM. Both IBM and we have been working independently on core technology, in our case for at least three years and IBM for more than that. So we believe that we will be uniquely postured through this joint development agreement. Beyond that I actually don’t know. We will probably hear more in the coming months from what our competitors are thinking in this space.

Editor: On October 8th, Cadence announced the availability of software that optimizes custom lithographic source illumination, a new capability in its integrated source mask optimization (SMO) technology family for IC manufacturing at 22 nanometers and beyond. Cadence collaborated with Tessera Technologies, Inc. to incorporate the custom source illumination manufacturing awareness into its SMO software technology family. The new capability is integrated into the Cadence resolution enhancement technology (RET) flow for both single- and double-patterning lithography. The collaboration between Cadence and Tessera focuses on Tessera’s DigitalOptics technologies, which provide
conventional, gray-tone, and free-form litho source illumination. Effective source mask optimization requires that the full degrees of freedom and actual constraints of the illumination design are incorporated into the design algorithms. Incorporating these more advanced models into the Cadence SMO software provides powerful new capabilities to the entire user community.

The top articles over the last two weeks as determined by the number of readers were:

Cadence Board of Directors Creates Interim Office of the Chief Executive; Michael Fister Resigns  Cadence announced that its BOD has formed an Interim Office of the Chief Executive to oversee the day-to-day running of the company's operations, effective immediately. The Interim Office of the Chief Executive includes: John B. Shoven, Ph.D., Chairman of the Board of Directors of Cadence, who has been appointed to the position of Interim Executive Chairman, Lip-Bu Tan, a director of Cadence since 2004, who has been appointed Interim Vice Chairman of Cadence's Board, and Kevin S. Palatnik,
Senior Vice President and Chief Financial Officer. Charlie Huang, Senior Vice President - Business Development, has been named Chief of Staff of the Interim Office of the Chief Executive.

The formation of the Interim Office of the Chief Executive followed Michael Fister's resignation as President, Chief Executive Officer and a director of the company, by mutual agreement between Mr. Fister and the Board. 

Apache Design Solutions Achieves Record Sales for the Twenty-Third Consecutive Quarters The Q3 growth came from increasing investments by existing customers that represent the top tier semiconductor companies and adoption by new customers facing power and noise challenges as they move towards 45/32nm technologies.

Berkeley Design Automation Delivers Industry's First Fractional-N PLL Transistor-Level Noise Analysis Berkeley announced the industry's first closed-loop noise analysis of fractional-N phase-locked loops (PLLs) at the transistor level. Combining transient noise and periodic noise analysis in the company's Noise Analysis Option™ device noise analyzer, designers can now optimize and characterize all fractional-N and integer-N PLLs for phase noise and jitter prior to silicon fabrication. The result is improved performance, lower power, and faster time-to-market.

Gemini Unveils Industry's Fastest SPICE-Accurate Analog Simulation Technology Gemini Design Automation, a start-up company focused on the challenges of verifying complex analog and mixed-signal designs, unveiled the industry’s fastest SPICE-accurate simulation technology specifically developed to leverage the throughput advantages of multi-core computing. The company’s native multi-threaded technology has demonstrated run times and capacity of up to 30x that of earlier generation analog simulators, and up to 10x improvements over first-generation multi-threaded approaches.

The MathWorks Enables Deployment of Parallel MATLAB Applications and Extends Parallel Programming Language With this new release, MATLAB users can convert parallel MATLAB applications into executables or shared libraries and provide them to their own end-users royalty-free. This is possible by running applications developed with Parallel Computing Toolbox through MATLAB Compiler. The resulting executables and libraries can take advantage of additional computational power offered by MATLAB Distributed Computing Server running on a computer cluster. As a result, a broad class of professionals
who do not work with MATLAB directly, are able to benefit from parallel MATLAB capabilities.

46th Design Automation Conference Names Executive Committee DAC announced the Executive Committee for the 46th DAC, which will take place July 26-31, 2009 at the Moscone Center in San Francisco. The Executive Committee is charged with overseeing the exhibition, planning the technical program, establishing new initiatives, and managing the conference’s operations and publicity. Andrew B. Kahng of the University of California at San Diego will serve as General Chair and lead the 46th Executive Committee.

Other EDA News

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-- Jack Horgan, Contributing Editor.

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