November 03, 2008
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Where does the competition stand versus Mentor’s current and future products?
I don’t really know. I have not heard about the competitive products in this realm. We believe that we have an early jump by virtue of our collaboration with IBM. Both IBM and we have been working independently on core technology, in our case for at least three years and IBM for more than that. So we believe that we will be uniquely postured through this joint development agreement. Beyond that I actually don’t know. We will probably hear more in the coming months from what our competitors are thinking in this space.
conventional, gray-tone, and free-form litho source illumination. Effective source mask optimization requires that the full degrees of freedom and actual constraints of the illumination design are incorporated into the design algorithms. Incorporating these more advanced models into the Cadence SMO software provides powerful new capabilities to the entire user community.
The top articles over the last two weeks as determined by the number of readers were:
Senior Vice President and Chief Financial Officer. Charlie Huang, Senior Vice President - Business Development, has been named Chief of Staff of the Interim Office of the Chief Executive.
The formation of the Interim Office of the Chief Executive followed Michael Fister's resignation as President, Chief Executive Officer and a director of the company, by mutual agreement between Mr. Fister and the Board.
Apache Design Solutions Achieves Record Sales for the Twenty-Third Consecutive Quarters The Q3 growth came from increasing investments by existing customers that represent the top tier semiconductor companies and adoption by new customers facing power and noise challenges as they move towards 45/32nm technologies.
Berkeley Design Automation Delivers Industry's First Fractional-N PLL Transistor-Level Noise Analysis Berkeley announced the industry's first closed-loop noise analysis of fractional-N phase-locked loops (PLLs) at the transistor level. Combining transient noise and periodic noise analysis in the company's Noise Analysis Option™ device noise analyzer, designers can now optimize and characterize all fractional-N and integer-N PLLs for phase noise and jitter prior to silicon fabrication. The result is improved performance, lower power, and faster time-to-market.
Gemini Unveils Industry's Fastest SPICE-Accurate Analog Simulation Technology Gemini Design Automation, a start-up company focused on the challenges of verifying complex analog and mixed-signal designs, unveiled the industry’s fastest SPICE-accurate simulation technology specifically developed to leverage the throughput advantages of multi-core computing. The company’s native multi-threaded technology has demonstrated run times and capacity of up to 30x that of earlier generation analog simulators, and up to 10x improvements over first-generation multi-threaded approaches.
who do not work with MATLAB directly, are able to benefit from parallel MATLAB capabilities.
46th Design Automation Conference Names Executive Committee DAC announced the Executive Committee for the 46th DAC, which will take place July 26-31, 2009 at the Moscone Center in San Francisco. The Executive Committee is charged with overseeing the exhibition, planning the technical program, establishing new initiatives, and managing the conference’s operations and publicity. Andrew B. Kahng of the University of California at San Diego will serve as General Chair and lead the 46th Executive Committee.
Other EDA News
Moai Electronics Accelerates Flash Memory Controller Tapeout With Cadence Logic Synthesis and DFT Solutions
Technology Luncheon and Panel Discussion to Focus on Low Power Design During GSA Semiconductor Leaders Forum Taiwan
Teradyne and Teseda Providing Time-to-Market and Yield Enhancement Solutions for the UltraFLEX and J750 Test Platforms
Movidia Selects Virage Logic's Intelli(TM) LPDDR Interface IP Solution to Meet Stringent Mobile Video Application Requirements
Mentor Graphics Announces Nucleus Platform Media Player for Rapid Delivery of Multimedia Applications
DFI Technical Group Releases Low Power Features with New DDR PHY Interface Specification Version 2.1
Web-Based Electronic Design Automation Tools for LUXEON Power LEDs Simplify and Speed Development of SSL General Lighting Solutions
Si2 Announces Sponsorship of 3-D Architectures for Semiconductor Integration and Packaging Conference
Accellera Announces Call for Nominations for 2009 Annual Technical Excellence Award Honoring Contributions to Electronic Design Automation Standards
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-- Jack Horgan, EDACafe.com Contributing Editor.
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