November 03, 2008
Computational Lithography
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Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Does anyone other than IBM have a similar offering?

I didn’t explain that very well. Our partner to deliver this solution is Mercury Compute Systems. IBM also manufactures cell processors themselves. We have a third party in addition to IBM, namely, Mercury Compute Systems. Several customers have adopted this technology in manufacturing.

Editor: Mercury provides a pre-integrated coprocessor acceleration (CPA) cluster comprising Cell/B.E. blades in an IBM BladeCenter H system. Customers simply connect the CPA cluster to their existing standard compute cluster using a standard Ethernet connection.

Would you expand on Mentor’s recent announcement regarding 22nm?

Going back to our discussion on lowering K1 or resolution lowering and the fact that in going to 32nm and 22nm the industry does not have access to lower wavelength or higher NA, we are looking for ways to enable this generation of technology without hardware. What we looked at with IBM was how we could do much more sophisticated engineering in the illumination space. I mentioned that the first RET method used in the industry was off-axis illumination. In that mode the light source that was shaped to go and impinge on the reticule, would be for instance instead of going from flash light being completely on, we would obscure the central region so we get an annulus or ring of light around
the outside edge. That is a very simple example. We realized that we can do much more complex interrogations of the intersection of design layouts with the illuminator to engineer that. The result is much more sophisticated illumination sources. The joint product that we are working together with IBM to develop and then bring to market will take a given design and an awareness of a model that will be used to pattern the wafers and to highly optimize the OPC pattern that the mask will use and the shape of the light in the illuminator far beyond something like a simple annulus.

We have pictures of sample outputs. They are highly non-intuitive distributions of light in the illumination source. The net is that you get simultaneous source and mask optimization on a per design basis. That will do a couple of things. We have already seen it deliver incrementally better process latitude in manufacturing for a given target design, for instance improved exposure latitude or depth of focus. In some cases at 32nm and 22nm, the industry has started looking at decomposition of layouts into two distinct mask patterns to better enable resolution but that of course comes at a severe cost. We have seen example at 22nm like in metal where a layout that without this technology
that would require two separate mask layers, say one that prefers layout in one optimization, say x, and the other in y. But by using this source mask optimization to engineer the mask and the source, equivalent or better CD control can be delivered with a single masking layer. That has huge cost implications.

Then there is a final one we started to interrogate. For several generations designers have been required to work with certain design restrictions imposed by the patterning process and these have become more and more severe. For instance, restricting design rules that limit certain spacing or pitches between lines because the lithography patterns process window is not sufficient. We have seen examples that with SMO technology those restrictions can be eliminated or narrowed in design space. So it gives the designers access to more degrees of freedom in how they will layout the design.

Is the output in the form of instructions to lithography equipment?

Good question. It is exactly that. It is actually two things. Number one it is a modified GDS to go to the fracture tools that will write a mask pattern that is consistent with how we do an OPC today. The second thing is exactly as you describe. It is a sort of map of intensity versus x and y locations that the scanner tool will deliver. So this technology is designed to work in conjunction with evolving capabilities that scanner providers have to deliver a highly pixelized intensity map to the reticule. It is software that is highly sophisticated to output an exact map that the tool will deliver.

You said that there were three leading manufacturers of lithography equipment. Does Mentor support all three?

Yes. Out current and future software will work in conjunction with all three of these suppliers.

Who are these suppliers?

Nikon, Canon and ASML.

Does your software accept input from various design flows such as Cadence and Synopsys?

Our software can use any of a variety of upstage design tools. They work both with the litho-friendly design offering that I mention and with the standard full chip flow. Any of these design tools is supported. All we need is a target design and the OPC model. The OPC tool merges that target with the model for the process and will output the post OPC GDS.

In what form does the user supply the target design?

Either in GDS or more commonly today in OASIS, a more efficient format.

Are there any foundry restrictions?

No, none what so ever. In fact this enabling technology going to 22nm is really targeted to be for all foundries and memory manufacturers.

Would the output of your product be any different, if the user knew the target foundry and lithographic equipment to be used?

No. The 193nm market is dominated by two of the three players. I do not know exactly where Canon is in terms of their market penetration. I do not know of any restrictions or any reason why the output of our software would not work fine with any of these suppliers.

It gets a little complex to look at the degrees of freedom in our output given the way we are constructing our software today. I don’t know how deeply to go into this. For a completely free form illuminator, at least Nikon and ASML we understand, will be delivering hardware modifications to equipment or new models that will fully utilize that. In the short term and absent the ability to have a free form illuminator, diffractive optical elements that are used in equipment today can be engineered in such a way that you can still get a huge variety of output shapes. The net result is that there is nothing that we believe will limit the ability for our instructions to be used by the
scanner equipment for 22nm.

Concerning the relationship with IBM, are they providing the test cases and are they involved in testing or are they working on algorithms and software development or both? What is the division of labor?

Sure. This is unique in our relationship with IBM. It is truly a joint development effort. We have a combined team of mathematicians and software developers from both sides that are working together in both our San Jose location and IBM’s Yorktown Heights T. J. Watson Research Center and their East Fishkill, New York Development center. We have bodies going back and forth, working on the core algorithms. We have a team of really remarkable mathematicians that have developed some of the core algorithms for optimization that are used in this technology. Beyond that we are certainly accessing their development environment to do just what you describe; develop test cases and early
validation of results.

Is there a target time frame for releasing this as a product?

Our target for full manufacturing is for sometime in early 2010. We will have beta software available in June 2009. Our first internal alpha software is coming out in the next month or two. But beta capability in June ’09 and full production support in early 2010.

We want to emphasize that IBM is not just a beta site for our software. It is truly a joint development effort where both companies will put IP into the product.

Where do you see 22nm adoption today?

The timing we have for our software we feel is consistent with leading edge customer needs. Certainly IBM is one of the first tier, leading edge customers. There are an increasingly small handful of others that are pushing the envelope on technology development. Right now there is a very early residue of design rules being formulated and that will be revised over the next several months at leading foundries and at leading microprocessor manufacturers; IBM and other places. The one thing that is very interesting is that typically lithography technology has gated the next generation R&D for processor development and in the past it has always meant that you are waiting. You pay your money and get in line for the next generation of scanners from Nikon and Canon. Everyone is sort of waiting on that. It is frequent that select customers will send development wafer off to the scanner companies to get on a prototype tool, to get early exposure. The nice thing (I guess it is a nice thing) is that with 22 nm the equipment is fixed. Lithography R&D groups have access to the patterning equipment. In fact work has been going on for nine months or so on 22nm patterning development. It is still very early on.
There is certainly no 22nm production. Our understanding is that 22nm production won’t start until late 2010 or early 2011.

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-- Jack Horgan, Contributing Editor.

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