September 29, 2008
SiP or System-in-Package
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor


by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


What is Cadence’s competitive advantage?

There is one big obvious difference which is Cadence is the only vendor that can provide an integrated chip design, packaging design and PCB design flow. We provide all three parts of that design flow. The second reason is because Cadence has IC design as part of our portfolio, we actually understand the whole need for co-design. In fact we were the first EDA company to introduce the idea of co-design between the IC team and the packaging team. We introduced that with our first SiP solution a couple of years ago. We were also the first to introduce a truly focused solution. We are the only one that supplies you chip design, packaging design and PCB design.


Also, the fact that we have such strong customer portfolio of IC companies, packaging foundries and system companies gives us an advantage of being ahead of where the market is going and where technology is going, so that we can provide solutions faster than anybody else.


Anything else to add?

People ask SoC versus SiP. It is not one or the other. They are complementary. They are time when you want to integrate functionality together a system-on-a-chip but there are also times when you want to add peripheral functionality that may change within a very short period of time like memory. That’s were SiP comes. Often you put a SoC into a SiP to complement the SoC with supporting silicon. It is not an either or proposition.


The top articles over the last two weeks as determined by the number of readers were:



IBM and Mentor Graphics to Develop 22nm Computational Lithography Solution for the Integrated Circuit Industry IBM and Mentor Graphics Corporation announced an agreement to jointly develop and distribute next-generation computational lithography (CL) software solutions to enhance the imaging capability of lithographic systems used in the manufacturing of integrated circuits at the 22 nm node and beyond. The agreement is part of IBM’s computation scaling initiative to create the industry’s first computationally based process for production of 22nm semiconductors, also announced


GateRocket Receives $3M In Venture Financing GateRocket today announced it has completed a $3 million Series-A round of financing led by New Atlantic Ventures, Massachusetts Technology Development Corporation (MTDC), and Long River Ventures. Seed-stage investors and Angel groups also participated to bring the total GateRocket has now raised to $4.5 million.


Fresco Microchip Selects Berkeley Design Automation Analog FastSPICE(TM) and Noise Analysis Option(TM) for Single-Chip Broadcast TV Receiver Berkeley Design Automation tools include Analog FastSPICE circuit simulation, Noise Analysis Option™ device noise analyzer, RF FastSPICE periodic analyzer, and PLL Noise Analyzer™. The company guarantees identical waveforms to the leading "golden" SPICE simulators down to noise floor (typically 0.1% or less) while delivering 5x-10x higher performance and 5x-10x higher capacity. It achieves this by using advanced algorithms and numerical analysis
techniques to rapidly solve the full-circuit matrix and the original device equations without any shortcuts that could compromise accuracy.



Liga Systems Opens East Coast Customer Support and Development Office Appointing Dr. Pranav Ashar as Chief Scientist and Team Leader The activities at this location will initially be heavily focused on R&D along field and sales support for our customers in the region. Already, five senior developers plus one Sr. Applications Engineer, all simulation experts, have joined Liga Systems at this location. The East Coast Office is headed up by Dr. Pranav Ashar, who has been appointed as Chief Scientist for Liga Systems.

Dr. Ashar’s role is to guide future technology directions and product development for the company. Prior to joining Liga Systems, during his tenure as Department Head at NEC Labs in Princeton New Jersey, Ashar lead the original team that invented the underlying core technology embodied in Liga’s hybrid simulator, NitroSIM. In addition, Ashar was co-founder and CTO at Netfortis, and CTO at Real Intent.


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-- Jack Horgan, EDACafe.com Contributing Editor.




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