September 29, 2008
SiP or System-in-Package
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Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
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In the ever difficult to define typical case, is package design a one person effort, a small team, a large team?

Good question. Compared to a chip team you are talking about a totally different kind of resource model. Where you might have 50 engineers working on the chip that go into a SiP, you are likely to have 3 or 4 people doing the SiP itself, doing the actual SiP implementation. You are talking on average about between a 5 to 1 and a 10 to 1 difference between the size of the chip design team and the SiP design team.

What does Cadence offer to those customers who want to design SiPs?

We offer technology. We have a full suite of tools not just for what I call traditional packaging design but also two solutions specifically for System-in-Package. We have a solution for those companies wanting to do large ASIC based SiPs where the focus is really about co-design. We also have a solution for analog/mixed-signal/RF SiPs, which is predominantly in the space for wireless multimedia headsets. There the focus is not so much on co-design but functional integration and simulation of those chips together with the discretes. You can actually build a true wireless front end in a package. So we offer two solutions there. Then for companies that are trying to do this for the first
time, we have a services offering through a group we call VCAD, which stands for Virtual CAD. They are a team of very experienced design engineers, who go into companies that are new to this area and help them build a reference flow and methodology and help them with a pilot project to take their first design through. We can offer the traditional EDA vendor approach of tools and technology or we can actually come, define a project, define some objectives and build a custom methodology plus train your engineers to put that flow in place. Basically hold your hand through your first project so that you can be successful.

Is more of Cadence business in this area on the ASIC side or the RF/mixed-signal side?

It is split pretty much 50/50. If you are on the wireless mixed-signal side, you really do not have an alternative with that market. People want so much technology in such small form factors, and at such a low price (think of the iPhone, Blackberry and other handheld PDA devices), that you have got to do a SiP. We have a huge user base there. On the digital side, I would say that there are companies that are fairly well established in doing SiPs but there are a lot of new companies coming on line, waking up to the advantages of combining silicon together on the digital side, predominantly memory; putting memory directly in there with any form of ASSP processor to improve the overall performance and reduce power between processor and memory. A lot of the traditional suspect players out there, who produce these large graphics processor chips as well as chips that go with your XBOX and PlayStation, where you are talking about a lot of digital power crunching going on. They are pretty well aware of the value of a SiP over the discrete packaging of the past. Our business is pretty well split. In the mixed-signal space, the guys are pushing the envelope but they are not only putting chips together, they are also putting discrete passive structures like antenna structure, passive filter networks, and tuning circuits. They are actually putting them down in the package level
and using them to affect the performance of the chip. They are doing very sophisticated chips. The digital guys are more creative and artistic in the ways they are leveraging the extra packaging real estate they get by doing a SiP.

How big is Cadence’s IC packaging and SiP business?

I am not allowed to give out any numbers in terms of any other area of Cadence business or a dollar amount. But if we talk about in relationship to our packaging business, Cadence is one, if not the largest supplier of SiP technology in the market. You talk about our SiP business being 30% to 40% of that packaging business. What is happening out there is that the packaging business is going through a change. The packaging business is basically moving up the food chain. We are seeing our traditional packaging customers starting to adopt SiP, primarily because their customers are demanding it. It is a new market for them to leverage extra value compared to their previous market of just
taking a chip and literally placing it inside a package. Now they are able to add value by integrating multiple pieces of silicon in a package. That’s a more valuable proposition to the market. Therefore, they can get more revenue that way. So they are going up the food chain at the same time. That’s why we are starting to see out overall packaging business number one in growth and adoption but also SiP because our traditional market is migrating to doing more SiP than standard fixed packaging.

Who is Cadence’s competition in this arena?

Who is the principal competition for us? There are really two companies. One is global. That company is called Sigrity. Then there is one company that is very specific to the Japanese market. That is called Zuken. There are lots of very small niche players, firms that are 100 times smaller in terms of revenue.

Have there been any recent product introductions by Cadence in this area?

We just announced our latest release of IC Packaging and SiP tools. We just released SPB 16.2. We announced that two weeks ago.

What were the highlights of that release?

Two big areas! First of all, we introduced our first package power delivery network solution. We talked earlier that one of the big challenges of SiP is power delivery networks, to provide power efficiently to low power chips. We announced our first true power delivery design solution for SiP. There were two other areas in that release. One was true constraint driven support for high density interconnect design, HDI. HDI, also know as microvia, is a manufacturing methodology for integrating chips and devices together at extremely small pin pitches. I am talking about 65 millimeter of pitch between the pins and smaller. That is the way you get true miniaturization. That is why going to
65 nm and 45 nm is allowed. At that scale of extremely small pin pitches, you can mount your silicon in the smallest possible space. But, of course, that puts some very interesting manufacturing constraints on the packaging team. They have to adopt what is known as high density interconnect buildup methodology in order to accommodate these micro pin pitch devices. What we have done is to introduce rules and constraint driven design approach dealing with HDI so that designers can focus on design rather than focus on doing all these manufacturing DFM checks to make sure that the design is in fact compliant with the HDI requirements. What we have introduced is very substantial.

Last of all, we did a partnership with a company called Kulicke-Soffa, also known as K&S, an American company. They are the world’s number one provider of hardware for packaging assembly. They provide the equipment that assembles the chip into the package. As we get into these complex SiPs, the need to be able to understand real manufacturing DFM data and take that into account is really important. If you do not do it, you either under-design because you have to apply very large tolerances for the manufacturing processes or you can sometimes get designs that are not manufacturable or have very poor yield.

A designer’s 3D view of a wirebond design using Kulicke and Soffa-supplied wire loop profiles, which enable DFM-driven design.

A designer’s 3D view of a wirebond design using Kulicke and Soffa-supplied wire loop profiles, which enable DFM-driven design.
What we did with K&S is to partner with them to develop a library of wirebond profiles. For most stacked chips, stacked multiple dies on a chip, you use wire bonding to connect chips down to the bottom of the package. You do that using a gold wire and a machine called the wire bonder. It kind of looks like a sewing machine and it stitches these chips down. As you stitch these chips down, you need to be able to accurately model the 3D shape and curvature of the wire to make sure that the wires do not touch, which could cause a short circuit or that the wires do not come too close to another object like another chip, because you cause the machinery to clip the actual chip that would cause a breakage and therefore you would get a really bad drop in yield. One of the things we did, which was driven by our customers, specifically the assembly and test customers, was to provide their customer with a library of these profiles that were fully validated and approved by the machine maker, the hardware assembly machine maker. When designers do design and start combining chips together in complex chips, they should understand exactly what wire profile the machine can use. They can go in and validate the actual design to see if it is manufacturable during the design aspect phase. They do not want to wait until they have completed the design to learn “ Oh, by the way, you can not really assemble this guy. You can’t do want you are asking for ”. They want to be able to give the designers that knowledge up front. So what we did was partner with K&S. They have provided us with a validated library of wire profiles included in our latest release of SiP tools. So the design engineer is now DFM aware right from the very get-go. We think that is going to help
people improve the yield and quality of their SiPs and at the same time give them the ability to minimize the overall form factor. They are able to accurately design from the manufacturing point of view. Those were the major sound bits of our latest releases.

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-- Jack Horgan, Contributing Editor.

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