September 29, 2008
SiP or System-in-Package
Please note that contributed articles, blog entries, and comments posted on are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Then you have areas such as medical where people are using SiPs. It is a pretty common methodology for getting the level of technology required. I am thinking about implementing biomedical devices such as pacemakers and defibrillators. As you can imagine, they are fairly small. Often they are not much bigger than a small matchbook. Yet they need to have a high degree of functionality, operate on a very low power and, of course, if you mount chips together inside a package, then the interconnect distances between those chips are very small. We are talking about a few tens of micros when you have chips together inside a SiP and where the interconnections between the chips are almost
completely contained inside the SiP with very few external interfaces. Obviously the external interfaces are like the sensors connected to the heart for defibrillator and cabling that goes to the battery unit that powers the device. But other than that, most of the functionality is going on in the SiP and because the chips are so close to each other, you can use low power drivers and receivers.

So you could end up with a very efficient solution not only for power consumption but also it generates very little em, very little electromagnetic interference, because you are really running at such low voltages. In the medical device area, most every type of biomedical implant you have has multiple chip sets in that solution. Plus, of course, having all of the chips together in a SiP means that once the SiP is tested, it is a pretty robust unit. All of the silicon is there inside a hermetically sealed package. It is nice and robust.

You referred to JDEC.

That is a standard body that defines the physical characteristics such as shape, size and pin locations of packages. Every IC package that you commonly use today goes back to a JDEC standard.

In addition to rapidly changing technology what else is going on that makes the design of chips more complex or challenging today as opposed to say 18 months ago?

One thing, of course, is low power. Preliminarily, it is due to the fact that, if you have a handheld unit, your want maximum battery life. But that aside, as you might have heard, a lot of people today have green initiatives. Companies want to leverage the fact that their products use less power than the competitors’ products. Therefore, there is less of an imprint on the environment, carbon dioxide emission for example. If you are going to start designing for low power, then the problem you have to tackle is concerned with the power delivery network. How do you get the power from the source efficiently to the chip so that you minimize the amount of lost power due to inefficient delivery methodology or due to the fact that you are delivering the power at the wrong impedance and therefore you are going to have to deliver more power because a lot of it is going to be wasted? Low power is another big challenge and that brings about the need to think about designing your power delivery supply system within the package. The PCB that the package sits on is also part of it. You need to design your power delivery network so that, first of all, you can provide sufficient power (of course, you can say that this is easy, as you can always crank it up) but secondarily and apart from sufficient power, you have to supply if efficiently. Do not oversupply and no do not undersupply. Make sure you can provide just the right amount of power that the chip requires. Next you have to look at stability, which happens to be the killer, because stability is keeping the power supply at a steady state voltage within a tolerance, that’s a ripple level, as the chip switch. So as the chip functions not everything in the chip is on at the same time. Different sections are switching on and off as different current demands for the package and the PCB. The trick is to develop your power delivery network structure in the package so that you supply the chip with the power that it requires, no more than it requires and no less and do that in an efficient manner so that the size of the package is as small as possible. That is one of the really big tricks because historically, when people build a package, they quite often over engineer their power delivery network so that the packages ends up bigger than it needs to be. The problem is that you have a lot of wasted power. The chip is fine, it functions great but you are over delivering the power. The problem is that you are wasting the power. There is a lot of leakage in the package. In today’s world of battery powered devices, people go shopping the look for EnergyStar efficient TV’s and refrigerators. The same holds for electronic subsystems. Companies are advertising that their network router that you
plug into you home actually consumes less power than the competitors’ router. The whole notion of being power friendly or green so to speak is another important aspect that is different to a world of three or four years ago.

You asked about other ones. The other one is high speed. If you look at the speed in which we are able to send data around in a system, two or three years ago we were talking about PCI Express Generation 1 at 3 1/8 Gigabits/sec. Now we are talking about 6+ Gigabits/sec as being fairly common. People are introducing things like 10 Gigabit Ethernet. When we have got this exponential rise in speed of signals that brings a whole new set of problems in terms of being able to design efficiently for bit error rates, to make sure that you meet various standard protocols that are required in these sorts of systems. Now almost all high speed interfaces are serial interfaces or SERDES devices. PCI Express is a very good one. There are other very common ones out there like SATA. The big challenge there, of course, is in maintaining the integrity of those signals, to get a bit error rate that is within the specification of the interface. If you look at PCI Express Gen 1 or Gen 2, they will tell you that between the transceivers you need to be able to pass data with no more that a certain number of dropped bits per million bits. So you need to be able to design and simulate that as you are constructing the package, to be able to look at eye diagrams, to be able to document and validate that you are actually meeting the PCI Express spec. The reason for that is that when you plug into a system, where you are talking to another transceiver that is PCI Express compliant, you will know that the system will function because you have designed your parts of the system to meet that detailed spec. That puts a lot of strain on the designer because we are caught in a plug-and-play world today. The whole idea of having these well designed interfaces is so that you can plug product from vendor A into a backplane from vendor B and providing they both claim that they meet the spec that is well documented, the system should function. That is a big challenge for the design engineer because he has to do simulation at the physical level, which means extracting interconnect models and
performing detailed SPICE level functional simulation to actually prove that he is meeting the spec.

Are the people who work with SiPs package designers or just designers that happen to choose SiP to implement a given design?

It is both. You have two kinds of camps. You have the IC company who is deciding how they are going to bring their technology to market. So very often the company will make the decision about how they want to package their silicon from whatever constraints they have, whether it is time-to-market, performance, cost. Then you have what is called packaging foundries and test companies that specialize in doing package construction. Here we are talking about people like Amkore Techncology, ASE Inc, and Stats, companies who have been for many years manufacturing the packages and doing the assembly and test of the packages. Think of a fabless model. People will come to these companies and say “I’ve got these chips. I want to put then into a package. These are my goals, what do you suggest.” The package company would say “Given your goals and boundary conditions (TTM,. cost, volume, etc.), we would recommend an implantation like this. ” It could be a SiP, a package-on-package, or many different things. Then you get the other side of the spectrum, the IC companies, the bigger companies; we are taking about STMicroelectronics, Texas Instruments, Qualcomm, and so forth. These guys have a lot of experience in packaging. They know that the packaging can influence their ability to win a certain market.
They decide themselves how they want to do the package and often design most of the package. Then they hand the package over to the assembly and test company and say “ This is my design. This is how I want it. I have looked at it from a signal integrity and power point of view. It meets my specs. What I need you guys to do now is optimize it for yield. Go in there and do whatever you need to do to improve the yield. The basic blueprint has been set by me.”

« Previous Page 1 | 2 | 3 | 4 | 5 | 6  Next Page »

You can find the full EDACafe event calendar here.

To read more news, click here.

-- Jack Horgan, Contributing Editor.

Review Article Be the first to review this article

ClioSoft at DAC

Featured Video
Senior Electrical Engineer for Allen & Shariff Corporation at Pittsburgh, Pennsylvania
Upcoming Events
DAC 2018 at Moscone Center West San Francisco CA - Jun 24 - 28, 2018
Symposium on Counterfeit Parts and Materials 2018 at College Park Marriott Hotel & Conference Center MD - Jun 26 - 28, 2018
Concar Expo 2018 at Convention Hall II Sonnenallee 225 Berlin Germany - Jun 27 - 28, 2018
Nanotech 2019 at Tokyo Big Sight East Halls 4-6 & Conference Tower Tokyo Japan - Jun 30 - 1, 2018
ClioSoft at DAC

Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise