May 19, 2008
Buzz@DAC & Kuhl@CAL
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Director of Marketing
* At DAC’08,
Synopsys will show the many ways you can count on us to be your primary vendor: for Hot Technology (IC Compiler, HSIM XA, Design Compiler Graphical and MVSIM); for Cool Solutions (Eclypse Low Power, Multi-Core Performance, VMM Methodology and Analog Mixed-Signal Verification); and for our commitment to the design community.
Senior Vice President of Marketing & Strategic Development
* Customizable EDA building blocks are changing the way people think about EDA. Instead of relying on one size fit all standard tools, EDA building blocks enables semiconductor companies to have their own customized tools that really address their needs. At DAC,
SoftJin will be demonstrating several of its high-performance EDA IPs across domains such as post-layout EDA, FPGA synthesis and routing. These customizable EDA IPs are helping our customers get advanced and proprietary functions in their tools and flows, thus helping create differentiation over their competitors.
Vice President of Marketing & Strategy
and communicating layout instructions accurate.
Imperas will be showing new products solving embedded software debug, verification, and analysis issues, particularly as these issues occur on multicore platforms. The new multicore debug and MIPS Linux developer workbench will be demonstrated including application debug on SMP Linux. Tools to build virtual platforms using SystemC and SPIRIT IP-XACT will also be shown.
Vice President of Sales
EVE, the leader in hardware/software co-verification, will showcase a library of standard transactors and a new custom transactor development tool at DAC. An AXI Master/Slave transactor and a PCIe Gen 2.0 16x transactor have been added to EVE’s standard protocol library. ZEMI-3, a transaction modelling methodology to create transactors for custom protocols, raises the abstraction level for hardware debugging.
Vice President of Worldwide Marketing
* Agreement grows on the importance of co-design of chips, packages and boards, but the modeling considerations can be confusing for design teams. Model availability, frequency dependent accuracy considerations and abstraction level are just some of the issues. This has led
Sigrity to support flows that run the gamut, while continually working to simplify user-level considerations.
Vice President of Sales & Marketing
* DAC’s Wireless theme fits well with
Agilent Technologies’ high-frequency background. High-frequency and high-speed design worlds are colliding where designs using multi-Gb/s data rates are seeing effects previously seen only in RF and microwave designs. At DAC, Agilent EEsof EDA is showing how its breadth of high-frequency simulators can be used to analyze the complete serial link.
Customer Communication Manager
EEsof EDA Division
ViASIC leverages reconfigurable semiconductor fabrics – slashing mask costs up to 95% versus a standard ASIC design approach, and reducing design time and risk in rad-hard, mil/aero and FPGA conversion applications. Visit our booth for a demo of ViaPath, our patented one-mask configurable logic and memory semiconductor technology. It offers the highest system density for embedded SOCs or structured ASIC fabrics.
President & CEO
Xilinx’ new ISE Design Suite 10.1 provides a unified design environment to help users maximize both design performance and productivity, whether their designs require a flexible embedded processing solution, a specialized flow for DSP development, or optimal high-performance logic. The ISE Design Suite includes PinAhead technology to simplify the complexities of managing FPGA to PCB I/O assignment for all designers.
Product Marketing Manager
ISE Design Tools
Micro Magic has improved our tool flow by adding support for OpenAccess. We have also added PCell interoperability through IPL PyCells. Curious engineers can register for Micro Magic's GDS and OpenAccess viewer – MAX-View – free of charge. Micro Magic has also added features to our unique datapath compiler DPC. This datapath tool provides higher-performance and lower-power for datapath intensive designs.
EDA Tools & Chip Design Services
* Launched in early 2008,
Mentor Graphics' inFact intelligent testbench automation solution is the first to use intelligent algorithms to synthesize meaningful testbench sequences, while allowing the user to set verification goals prior to simulation and determine verification priorities. The inFact algorithms rapidly generate test sequences, data, and checks on-the-fly during simulation, achieving the highest levels of functional coverage and early detection of design bugs.
Product Marketing Manager for inFact
Certess, the provider of functional qualification solutions for SoCs and IP blocks, will be showcasing Certitude and Certitude-SV. Certitude provides verification engineers with an objective way to evaluate and improve the completeness of the verification environment, resulting in shorter and more predictable process to integrate SoC designs. Certitude easily complements all existing verification environments. Certess will also be hosting several customer and industry leader presentations in their booth. Space is limited for customer presentations so please register in advance. If there was a bug in your design, could you find it? Visit our booth at DAC and find out.
President & CEO
Verific Design Automation is Head and Shoulders above the Rest. We offer SystemVerilog and VHDL front ends for EDA developers. Check out Verific’s Wall of Fame in our DAC booth, and see the 50+ logos of companies that standardize around our parsers and elaborators. Or, walk the show floor and come across several of Verific’s 20-something licensees exhibiting at DAC this year. You’ll agree: Head and shoulders above the Rest!
Verific Design Automation
Satin IP Technologies is a first-timer at DAC. We will demo VIP Lane, a Design-for-Reuse Assistant enabling semiconductor companies to deploy their home-made design-for-reuse methodology internally, with maximum adoption rate by the design teams. What makes VIP Lane hot and innovative? It supports proprietary design-for-reuse practices, offers checklist-driven assistance to IP designers, and monitors IP quality closure on-the-fly.
Founder & CEO
Satin IP Technologies
Atrenta helps customers get their designs right, at RTL and earlier, to speed-up implementation and verification. We call it Early Design Closure. The benefits? Better performance, predictable schedules, and reduced design risks. We'll announce a new architectural-level product before DAC, and pre-packaged methodologies at DAC. A comprehensive tool suite and proven methodologies for easy adoption - Early Design Closure for everyone.
Vice President of Marketing
Visit our website to sign up for a suite appointment at DAC.
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-- Peggy Aycinena, EDACafe.com Contributing Editor.
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