May 19, 2008
Buzz@DAC & Kuhl@CAL
Please note that contributed articles, blog entries, and comments posted on are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Brett Cline

Vice President of Marketing & Sales

Forte Design Systems

* Recently,
Kilopass was the first to complete qualifications of its high density embedded non-volatile memory technology, called XPM (X-tra Permanent Memory), at 90 nanometers and 80 nanometers. These qualifications support OTP (one-time programmable) configurations up to 128K bits for CMOS SoC applications. Additionally, in the run up to DAC, XPM has already been taped out by multiple customers at 65 nanometers, and will complete 65-nanometer qualification of its XPM technology soon after DAC in July 2008.

Craig Rawlings

Director of Marketing

Kilopass Technology

Apache's Chip Power Model (CPM) won the
EDN Innovation of the Year award for 2007 in the EDA category. CPM is a compact and accurate Spice compatible model of the IC's power delivery network and is one of the key technologies in the company's Sentinel product line, a chip-package-system co-design and co-analysis solution that we'll be highlighting at this year's DAC. Chip-package-board co-design is becoming a hot topic these days as issues of power and signal integrity are no longer contained or isolated between the IC and package/board. We're hearing from customers like ST, TI, and Toshiba that co-design is one of the key requirements for improving productivity and lowering cost.

Dave DeMaria

Senior Vice President of Chip-Package-System


Ciranova is introducing the industry's first automated analog layout solution, called Helix. Helix produces design-rule-correct placement in minutes and enables analog IP migration. It optimizes both circuit and device layout simultaneously, delivering design-rule-correct placement comparable in quality to that produced by an experienced layout designer. Using Ciranova Helix, analog and custom designers can explore multiple layout alternatives in minutes, allowing them to get higher-quality designs to market in a fraction of the time needed by conventional methods.

Dave Millman

Vice President of Marketing


* Denali Software
will be highlighting our selection of industry-leading EDA and high-quality standards-based IP solutions for DDR3 and PCI Express 2.0, support for SystemVerilog-based methodologies and verification IP for all protocols, and our new FlashPoint PCIe NAND Flash platform solution. Schedule a meeting with our experts, or register for the famous
Denali Party at DAC!

David Lin

Vice President of Marketing

Denali Software

Javelin Design
Automation unveils the first
Specification-Driven floorplanning and
prototyping family for early design feasibility from spreadsheet, black-box, ESL, partial and dirty RTL through to netlist.
j360 TrueFit,
TruePlan, and
TruePro enable business users, architects, logic designers and chip integrators to predict, see, fix, and optimize SoCs closeability earlier in the project cycle. High-Performance-Teams use j360 to achieve challenging targets in less time.

Diana Feng Raggett

President & CEO

Javelin Design Automation

CebaTech develops and markets ESL tools for advanced ASIC, FPGA and SoC design, and uses these tools to create and license high-value IP cores. Visit us in our booth to see demos of our C2R Compiler with both data path and control path dominated designs, and discuss our current and future IP cores for the networking, storage, communication system and server markets.

Elaine Jones

Vice President of Marketing & Business Development

CebaTech Inc.

IC Manage will demonstrate its design data management, project management, and design IP reuse solutions at DAC. IC Manage offers advanced revision control, hierarchical IP-based configuration management and design IP reuse capabilities, and includes out-of-the-box integrations with EDA environments (including Cadence/Synopsys) and issue management/bug tracking systems (including Bugzilla/JIRA). IC Manage addresses the extreme performance, capacity, scalability, and reliability requirements of globally distributed design enterprise. Visit us in our booth.

Dennis Harmon

Vice President of Business Development

IC Manage

Gradient Design Automation pioneered accurate, fine-grain IC thermal analysis that produces a 3-dimensional temperature map of a chip. Gradient’s products fit into the standard EDA flows, and help to expose thermally induced circuit failures and performance degradations before tapeout, so that corrective actions can be taken. By adding temperature-awareness to the design flow, Gradient improves circuit simulation accuracy and exposes opportunities to neutralize the temperature effects, as well as improve the chip design.

Ed Cheng

President & CEO

Gradient Design Automation

ATopTech launched in December 2007, and will be showcasing for the first time at DAC, the company's flagship product, Aprisa. Aprisa is a complete netlist-to-GDSII physical design solution, including floorplanning, placement, clock-tree synthesis and optimization, global and detailed routing, and an extremely fast timing engine to handle complex timing challenges such as OCV and MCMM. Aprisa uses state-of-the-art multi-threading and distributed processing to further speed up the process and avoid the exploding runtime issues with modern nanoscale design. Contact us to set up an appointment.

Eric Thune

Vice President of Sales & Marketing


Bluespec invites you to come see synthesizable models and testbenches running 35,000 times faster than event-driven simulation, our new development workstation, and Nikhil and Arvind at Sunday's high-level synthesis workshop. Come see atomic transactions for hardware – there's a reason we've picked up six new tier-one customers this year, and why we're the only general-purpose high-level synthesis solution for synthesizable models, testbenches, and control and algorithmic IP.

George Harper

Vice President of Marketing


Concept Engineering develops and markets innovative visualization and debugging technology for commercial EDA vendors, in-house CAD tool developers, and IC and FPGA designers. We will be showcasing all of our visualization and debugging products at DAC, including: Nlview Widgets - a family of visualization engines for EDA tool developers (Tcl/TK, MFC, Qt, Java, Perl/Tk, wxWidgets), SpiceVision PRO - a customizable debugger for SPICE and DSPF based designs, RTLvision PRO - a graphical debugger for SystemVerilog, Verilog and VHDL based designs and GateVision PRO - a customizable debugger for Verilog, LEF/DEF and EDIF based designs. Stop by and visit us in our booth.

Gerhard Angst

President & CEO

Concept Engineering

Esterel EDA Technologies signed corporate deals with Texas Instruments and STMicroelectronics last December. This follows several successful projects with Esterel Studio in 2007 at these two major companies. In term of technology, Esterel Studio 6.0, comes with a performance estimator that guides new users unfamiliar with ESL control synthesis in comparing micro-architecture choices, balance between area and speed, and a check that they have not generated unwanted logic.

Günther Siegel


Esterel EDA Technologies

Spatial is a first-time exhibitor at this year's DAC. We are a market-leading provider of 3D software components for technical applications, providing 3D software and consulting services to EDA industry leaders like Agilent, Ansoft, CST, Synopsys and Zuken. We will be demonstrating a new, integrated solution tailored specifically for the needs of EDA 3D analysis developers, which enables rapid development of 3D analysis and visualization features within current physical EDA flows. Come see us in our suite at DAC.

Howie Markson

Director of Marketing


* Do you suffer from memory loss? Talk to
Sidense at DAC. We’ll show you how SiPROM and our new low-power SLP one-time programmable (OTP) memory IP can enhance your chips in a wide range of digital and analog applications, providing secure, high-density and reliable embedded storage. Hear us talk and meet with us at the booth, and catch the Sidense/ breakfast panel Wednesday morning. Our goal: OTP on every chip.

Jim Lipman

You can find the full EDACafe event calendar here.

To read more news, click here.

-- Peggy Aycinena, Contributing Editor.


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