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April 07, 2008
A Busy Day for Magma Design Automation
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


February 27th was a busy day for Magma Design Automation. They announced they had acquired Sabio Labs, introduced Titan full-chip mixed-signal design, analysis and verification platform, and launched QuickCap TLx, adding advanced transistor-level extraction support to its gold-standard 3D capacitance extractor. I had an opportunity to talk about the first two items with Ashutosh Mauskar, VP of Business Development at Magma.

Would you provide us with a brief biography?

I have been with Magma for the last nine months. I have been in EDA for 16 years. I have three patents and a master’s degree in EE. I have worked for major EDA companies.

Which ones?

Cadence and Synopsys

What is your current title at Magma?

I am Vice President of Product and Business Development.

What does a VP of Product and Business Development do?

I am responsible for business development activities for the entire Titan platform; product marketing, product rollout, development plan, all that stuff

Can you tell us about Titan that Magma recently announced?

Magma has announced our new product platform for mixed-signal. The name of the platform is Titan. The reason for that is pretty simple because if we look at the history of Magma, we have brought automation to the digital side. We introduced physical synthesis basically combined synthesis and physical synthesis together. If you look at the analog side, things have not really moved in that direction for a long time. If you look at the state of the art of analog technology, you are talking about 180nm and 130nm. If you look at the state of the art of digital technology, it is 45nm and 32nm. The reason for that is very simple because there is automation on the digital side. You bring your RTL and you synthesize to place and route. You have turnaround time from RTL to netlist in two or three days or perhaps a week at the most. But if you look on the analog side, the process migration of a design could take anywhere from six to twelve months depending on the complexity of the design. And then additionally the chips are mixed-signal nowadays which means integration of digital and analog full custom can take another four to eight weeks. If you look at the productivity of pure digital design and the productivity of mixed-signal design, the long pole in the tent besides integration are analog full custom as well as the design of analog full custom. There is no automation for that yet. There are reasons why they are not there. If you look at the way analog custom design is done today, you start with system design. You basically draw some Excel, AMS sort of specification. You verify these specs using C, MatLab or SPICE or something. Basically when you start with circuit design you have code where your system design works, then you restart your work drawing from schematics, writing specs from MatLab, Excel or paper and then capture the schematic. You SPICE the schematic making sure that it is verified and then finally you do physical design; manual design, constraints, placement and routing, extraction so on and so forth. For every node from 180nm to 130nm to 90nm to 65nm, you have to restart doing the design each time. You have to recreate every step which is either system level or circuit level or physical level design by hand. For every new node designs have to be recreated by hand from scratch. The issues become how accurate the transition is going to be, how automated is it going to be, whether you can have any reuse, whether there is any compatibility issues and so forth. In order to take care of all these issues, it typically takes designers anywhere between six to twelve months. Automating that is a very hard problem to solve, the kind of problem that Magma likes to solve. That is why we have introduced a new platform, called Titan, which is a
full chip mixed-signal design platform. We implement complex mixed-signal designs using a single platform. It allows you to improve your productivity by orders of magnitude by delivering unprecedented integration and automation to analog design.

What are the different components of Titan?

The key Titan technology components are essentially standard things that you would find in a full custom analog design environment which are schematic editor, simulation environment, IP process migration.


I am sure that you have heard that we recently bought a company by the name of Sabio Labs. It is an IP design as well as automation company. It allows us to take high speed components such as SERDES, ADC, DSC, PCI Express or PLLs and model them in one process using process independent circuit equations and migrate to another process node such as 130 nm to 90nm to 65nm using those process independent equations and providing you the flexibility to explore different options when you do the process migration.

Editor: Magma acquired Sabio Labs. The purchase price was $17.5 million plus possible additional payments up to $7.5 million based upon contingencies. Investors in Sabio Labs include Andy Bechtolsheim. The CEO of Sabio Labs is Mar Hershenson. She did ground breaking work at Stanford University under Professors Boyd and Lee in the area of automation of analog circuit design using convex optimization. In 1999 she and Professor Boyd formed Barcelona Design Inc based on that work. She became CEO and later shifted to CTO. Barcelona was notable for having raised $44 million in venture funding, for having Joe Costello as chairman, and having a Web-based pay per use business model.
Barcelona had two products, namely, Picasso Op-Amp Design and Dali PF Passives Designer. The technology automatically generated an optimized netlist from user-defined specifications. The company encountered difficulties and despite changing strategic direction and adopting a more traditional EDA business model the company ultimately closed its doors.

In our layout editor we have a shape based router. We have integration. That is the important part. This is a single platform that allows you to look into your digital as well as your analog pieces together. In a single canvas you have full on layer visibility, the digital part as well as the analog part. That is something that has never happened before. That is something that is very unique to the platform.

In this IP migration, if I already have an analog design and want to migrate to a new process node using the technology from Sabio Labs, do I have to convert that existing design into these circuit equations?

Yes! There is a one time issue of conversion of existing IP. And that is the beauty of it. We are basically freeing up analog designers to create ever new IP using their inherent artist techniques for analog designs. There is no way we can always replicate that. Obviously designers have years and years of experience. What we really want is for analog designers to be free to create new designs as opposed to just migrating the same designs over and over again. The idea is that if you create a PLL, you capture that PLL at one process node, say 180nm, you capture the topology of the PLL in terms of equations at the beginning of the process and then you can just migrate seamlessly from
one node to another to another. That’s the whole point of doing that.

But there is a one time conversion for an existing design from its original form to these equations.

Yes! In fact when we talk to our customers that is what they want. Obviously we provide standard templates for PLLs, SERDES and stuff like that. That is not very helpful because each analog designer takes pride in the fact that he or she has tuned the circuits to their own satisfaction and for their own requirements. It is actually a good thing we had to do this because that way they can capture their own specifications and topology.

What is special about Titan that you won’t find in other platforms?

We have FineSim integrated simulation environment, IP process migration in terms of automation. We have integrated the digital and custom analog flows seamlessly. Along with FineSim which is a full SPICE and fast SPICE simulator, we have integrated full Talus which is our digital design solution. We have integrated Quartz DRC and Quart LVS verification solutions. Last but not least the speed and capacity of the platform is pretty high. We have seen improvements up to 10x over existing solutions. It allows designers to integrate quickly the entire chip. There is a smooth migration path because it is important that designers who have labored for years and years want to have the ability to
smoothly migrate from existing environments to Titan. We provide that path for our customers.

FineSim SPICE is the fastest SPICE simulator. It is fully integrated with analog simulation environments. We have layout editors, simulators, … All these environments are completely integrated within Titan and can be invoked within Titan and be executed. The early FineSim customers include Toshiba, Maxim, Faraday, AMD, STARC and Sigma Design. FineSim also happens to be the fastest growing product within Magma at this point in time.

The second piece of the puzzle is fully integrated custom analysis for signoff as well as for DRC and yield. We have integrated our DRC and LVS. We are looking at full tight integration where you can have your own DRC errors, fix them and step through the DRC of your design incrementally. One by one you can fix all of the DRC errors. You can walk them through Titan incrementally and very seamlessly. Once you do your design, you can fix it very quickly. Quartz DRC/LVS platform is completely integrated within Titan. We are also looking to integration of noise and power.

We have taken a modern approach to this issue of analog IP process migration by allowing the designer to write a specification in terms of technology independent equations, analyzing the circuit using those resulting equations. The process migration engine and optimization engine will implement and optimize it. Finally as a result of that designers can reuse it many, many times by just changing the specification of the process nodes. You can change the constraints that you give to the process migration engine. You can change the library you feed to the optimization engine. Out come the schematic and layout constraints for your particular application. The process of migration becomes
very simple. Now as we discussed there is always a one time issue of converting your existing design into process equations. That’s a good thing because that way you can capture your own particular IP. Design managers and executives especially like it because now they get a way of capturing analog IP independent of the designers. Now they can preserve that IP for a long time. Many times you want to teach new generations of analog designers how you do it and for that you require a knowledge of what the circuit topology is which is universal and can be translated and migrated seamlessly in an equation based approach.

Titan is a true mixed-signal platform. Talus is our digital platform. Talus is completely encapsulated and embedded within Titan. That’s the key message.


Consider the image of the digital design shown above. The cell that is highlighted is a standard cell. You can see the internals of that cell with all layer visibility. You have full custom layout capability for the digital design. You can actually dive into the custom parts within the design. In this case the custom part happens to be a standard cell. Imagine instead of a standard cell, it could be an ADC, DRC or PLL. You can quickly dive into it in the same context and in the same camera; a true mixed-signal environment. We call this Live Integration because any change you make on the digital side is actually made live in the digital data base. The data base is unified for digital and

If I am making a change to an analog section because of an ECO, an interface issue or whatever, what design tool am I using, the original design tool or Titan?

You are using Titan. You do not need any other tool but Titan for either your digital part or your analog part. Titan embeds completely the digital part of Talus and BlastFusion point of view and allows you to do analog full custom design.

We have a full high speed and high capacity layout and schematic editors embedded within Titan. You can have responsive all layer drawing, panning, zooming, menus, hot keys and so on and so forth. To give you an example of speed and capacity of Titan for layout editing we read in a 42GB GDSII file of around 800 million transistor netlist. That netlist was converted into our database. The full chip open time was four minutes. Redraw time was 8 seconds. Zoom in time by 2 was 4 seconds and pan time to random points was 7 seconds. You may ask the question “So what?” If you look at the existing environments it takes more than 7 or 8 hours just to read in a 42GB design file. To
redraw, pan or zoom takes 15 to 20 minutes depending on what you are doing. You can easily appreciate the fact that designers do many of these things during circuit design. When you are doing these kinds of things repeatedly, these 15 to 20 minutes add up to something quite significant from a productivity point of view. This is a very high speed, high capacity system compared to what you have out there today which is essentially a very good system for 20 years ago but it is now getting old.

The next piece of the puzzle is new shape based and chip connection router. This is a brand new router specifically designed for Titan for mixed-signal chip finishing and assembly. It is a different router than we have in our digital data base. It is basically a shape based router unlike our digital router which is a grid based router. It is built for modern design and modern nanometer geometries. It supports schematic driven layout. You can put constraints on your schematic and automatically build constraints that get transferred to the layout. The router knows about these constraints and routes accordingly. These constraints could be that I want this length to a particular length or
be a particular RC value or this length must not exceed certain minimum and maximum values. Or maybe I need shielding for this particular net. You can put in all sorts of the analog full custom constraints. Then we have analog/digital global routing at the same level. This brand new router is part of Titan.

To recap we have a full schematic layout editor, a full shape based router, IP process migration technology, integration with our digital and full custom analog and integration with DRC and LVS. Essentially you have a full system for mixed-signal design from scratch in the form of Titan. That is what Magma has entered into. It is a mixed-signal design platform, which integrates the digital and custom together.

We have OpenAccess link for existing migrations. Our flow is very open to imports and exports. We support PCells, PyCells and OpenAccess. Obviously we have our own internal data base but we can read and write OpenAccess seamlessly without any issues. Our link to Volcano, our digital data base, is very light. We support LEF, SPICE and all the other inputs.

If you look at Magma in 1Q 2008 we have fundamentally a digital design platform. Now we are adding analog to it in terms of schematic capture, IP process migration, circuit simulation and so forth.

The reason we have process migration in Q1 is that we bought Sabio Labs two weeks ago. It will take some time for us to integrate it but the product itself is ready. It is already being sold stand alone. The integration piece might take another 2 or 3 months. By summer time we will have the entire platform.

Are the primary target applications ones that are incorporating existing analog designs or are you also targeting users who would be staring from scratch to design analog components SERDES for example?

Obviously, if you are stating up fresh, there is no problem. That’s the easiest thing. You can start with equations from scratch but if you have legacy designs that works too.

Analog designers have been using certain tools for years. Is the sweet spot for Titan the analog designers starting new designs or mixed-signal designs incorporating existing analog components?

If you are a pure analog IP house, then we can help you with your IP process migration. But initially we would target the big “D”, big Digital, small “a” for analog. That would allow us to coexist with the analog and digital worlds for a while. We do not expect this to be an overnight migration. We do expect there to be coexistence for a while and from there we go on.

Who is the competition?

Virtuoso platform from Cadence.

Why is Titan better than Virtuoso?

New architecture, new router plus automation of IP process migration plus constraint driven layout and shape based editing which provides the automation. As a result it improves the overall process significantly for designers.

What is the price point for Titan?

We have not disclosed that.

What did Sabio charge for its product?

They have not disclosed that.

How large a company was Sabio when Magma acquired it?

9 people

How large a customer base did Sabio have?

We have announced one of their customers which is MEI (Matsushita Electric Industrial Company Ltd). There are several more. Currently there are less than a dozen Sabio customers working on the Titan platform, 9 or 10.

Any beta sites?

We have not disclosed any beta sites. The only customer name that came out in this entire process is Matsushita.

Recent EDA Acquisitions

There were two major EDA acquisitions at the end of March.

On March 31st ANSYS, Inc announced a definitive agreement to acquire Ansoft Corporation for a purchase price of approximately $832 million of which $416 million will be in cash. The boards of director of both firms have approved the transaction. Ansoft will be become a wholly owned subsidiary. The firms had combined trailing 12-month revenue of $485 million. The firms will have about 1,700 employees. Both firms are headquartered in the Pittsburgh, Pennsylvania area. For ANSYS, a leading MCAE (Mechanical Computer Aided Engineering) company this will be its first foray into EDA. In the past few years ANSYS has acquired several MCAE companies including Fluent and Harvard
Thermal in 2006 and Century Dynamics Inc (CDI) in 2005. Ansoft will increase ANSYS’ annual revenue by about 25%.






























On March 20th Synopsys, Inc announced a definitive agreement to acquire Synplicity, Inc. Under the terms of the agreement, Synopsys will pay approximately $227 million or $188 million net of cash acquired. The transaction is subject to regulatory and Synplicity shareholder approval, as well as other customary closing conditions, and is expected to close in the second calendar quarter of 2008. After the closing, Synplicity will become part of Synopsys and Synplicity stock will cease trading. Synplicity is a leading supplier of innovative FPGA and IC design and verification solutions that serve a wide range of communications, military/aerospace, semiconductor, consumer,
computer, and other electronic applications markets. Synplicity also offers hardware-based rapid prototyping having itself acquired HARDI Electronics AB, a developer of off-the-shelf ASIC prototyping boards, for $24.2 million in cash in June 2007.






























These two acquisitions reduce the number of publicly traded exclusively EDA vendors with significant revenue to a small handful. Beyond the top four vendors Altium and Zuken spring to mind. Agilent EEsof is a significant player in the EDA arena but is part of a larger company. MatLab has significant revenue in EDA but is not publicly traded. If you include IP firms in the EDA mix, there are another half dozen led by ARM, Rambus and MIPS.

An Andy Rooney minute.

Voicemail is a tremendous invention and like most great invention the maximum benefit is obtained when it is used properly. Have you ever received a voicemail message “Hi this is Fred. Give me a call.” Fred who? At what number? When would be a good time to reach Fred? What is the call about? Is this really important requiring immediate attention or just an anything new type of call? If you recognize who Fred is, you are likely to engage in a lengthy game of phone tag. Ultimately you may find out that Fred wanted some information that you could have quickly and easily given him in an email or voicemail. Since the caller is initiating the contact, is it asking too
much for that person to provide some basic information?

What about the callee? The typical answering machine says something like “I am either away from desk or on another line. But your message is important to me, so leave you name and number at the beep and I will get back to you.” I often wonder if this is an honest statement. How could the callee know that the next phone is truly important to him? And if it were important, would he not make a better effort to receive it. Also is the person really just away from the desk or on another line. Might he really be on vacation, out sick, away on a trip possibly overseas where access to voicemail and email might be difficult not to mention the time difference? In one case I
finally learned that a person I was trying to reach had left the company but was still in the company’s telephone directory. The caller may try multiple times over the course of several days to reach the person who is not there to take the call. There is no way for the caller to know if the callee has actually listened to the voice message.

When I worked for IBM, they wanted their people to change their voicemail message everyday. “Today is April 5. I am in the office today but away from desk ….” If you heard an out of date message, it was likely the person was not in the office. IBM also required you to have different messages if you were on vacation, on a trip, and so forth. Customer facing personnel and others would leave a second number where a caller could reach a person who is expected to be in the office.

It is a bit late for New Year’s resolutions but perhaps we could make an effort and do ourselves and others a favor and commit to using voicemail properly.

The top articles over the last two weeks as determined by the number of readers were:

ANSYS, Inc. Signs Definitive Agreement to Acquire Ansoft Corporation see above

Synopsys to Acquire Synplicity, Inc. see above

Xilinx Delivers Complete Design Tools Suite - Providing Breakthrough Improvements in Productivity, Performance & Power Xilinx introduced the delivery of its ISE Design Suite 10.1, a single unified release providing FPGA logic, embedded and DSP designers with immediate access to the company's entire line of design tools with full interoperability. The ISE Design Suite 10.1 delivers significantly faster implementations with an average of 2X faster run times, allowing designers to complete more turns
per day. Significant to the release is the introduction of SmartXplorer technology, developed specifically to address the top challenges of the design community - timing closure and productivity. SmartXplorer technology leverages distributed processing across multiple Linux machines to enable even more implementation runs per day, and up to 38 percent faster performance by leveraging distributed processing and multiple implementation strategies. SmartXplorer technology also provides tools that allow users to monitor each run with individual timing reports.

Ciranova, Inc. Secures $5.25 Million in Funding Ciranova, an EDA start-up developing OpenAccess-based interoperable layout technology for analog and custom integrated circuit design, announced that it has closed a round of financing totaling $5.25 million. Industry leaders Synopsys and Mentor Graphics both participated in the round, along with previous investors Alloy Ventures (lead investor), US Venture Partners, Asiatech Management and Cadence founder Jim Solomon.

TSMC First to Deliver 40nm Process Technology The new node supports a performance-driven general purpose (40G) technology and a power-efficient low power (40LP) technology. It features a full design service package and a design ecosystem that covers verified third party IP, third party EDA tools, TSMC-generated SPICE models and foundation IPs. First wafers out are expected in the second quarter of 2008. The 45nm node provided double the gate density of 65nm, while the new 40nm node features
manufacturing innovations that enable its LP and G processes to deliver a 2.35 raw gate density improvement of the 65nm offering. The transition from 45nm to 40nm low power technology reduces power scaling up to 15 percent.

Other EDA News
  • NXP Semiconductors and IPextreme Launch Ground-breaking Methodology for Semiconductor IP Design
  • LogicVision Q1 2008 Conference Call Scheduled for April 22, 2008
  • Virtutech to Participate in Four Presentations and Panels on Multicore Software Development and Simulation at Multicore Expo 2008
  • Synplicity Announces Immediate Support for Xilinx Virtex-5 FXT FPGAs
  • Synopsys' New DesignWare IP Significantly Simplifies Transition to PCI Express
  • PLX Technology Adopts Cadence Incisive Palladium II Accelerator/Emulator for Full System Verification
  • ASSET® is first to support Intel®’s new Atom™ processor with CPU emulation test and diagnostics
  • Springsoft and Novas Agree to Merge
  • Silicon Canvas Attends SNUG, Demonstrates How Laker’s Interoperability Improves Custom IC Design Flows
  • Tensilica Selected for Multiple Presentations at Multicore Expo
  • EEMBC Launches Independent Benchmark Testing Service
  • New MultiBench(TM) Multicore Benchmarks Now Available From EEMBC(R)
  • Mentor Graphics Announces Synthesis Support for Xilinx Virtex-5 FXT Field Programmable Gate Arrays
  • LogicVision Receives Letter From Nasdaq Confirming Compliance with Minimum Bid Price Rule
  • ANSYS, Inc. Signs Definitive Agreement to Acquire Ansoft Corporation
  • More configurations for the audio CODEC from Dolphin Integration proven with 100 dB
  • Toshiba And Ponte Team On Advanced DFM Technologies
  • BellwetherReport.com Free Analyst Review for ACTU, ANST, SGP and MRK
  • Tensilica's New GUI Helps Cut Chip Energy Consumption
  • EVE to Demonstrate ZeBu at SNUG Interoperability Fair
  • Synopsys Extends Design Compiler Topographical Technology to Predict and Alleviate Routing Congestion
  • Synopsys Star-RCXT Extraction Product Delivers 2X Performance Boost With Dual- Core Support
  • HP Keeps Computing Personal With Digital Storage First and Customizable PC Lineup
  • Blue Pearl Software Announces Azure Timing Constraint Validation
  • Virtutech Presents Simics 4.0, First Deterministic Multithreading VSD Platform
  • Tensilica CEO to Discuss Energy Breakthroughs in Chip Design at Globalpress Electronics Summit
  • HP Introduces Servers, Customer Management Portfolio to Reduce Costs for Midsize Businesses

    Other IP & SoC News

  • Micron Technology, Inc., Reports Results for the Second Quarter of Fiscal 2008
  • Samsung Launches Lowest Powered, Highest Density DDR2 Memory for Servers
  • VMETRO Expands Buffer Memory Products to Include XMC Modules
  • Cypress PSoC(R) CapSense(TM) Interface Selected To Implement Touch-Sensitive Controls on JVC's Super-Slim Everio Hard Disk Camcorders
  • Avago Technologies Announces Enhanced Three-Channel Encoder for Use in Industrial Automation Machines
  • PulseCore First to Offer Spread Spectrum EMI Reduction for USB
  • MathStar Releases Second Generation MPEG-2 Encoder IP Core for the Arrix(R) Family of FPOAs
  • Pixelplus Obtains a Complete Victory at the Intellectual Property Tribunal of the Korea Intellectual Property Office on the Cancellation and Invalidation of the Disputed Process Patents Claimed by MagnaChip
  • OmniVision and Mobilygen Provide H.264-Based IP Camera Reference Design for Low Light Security Applications
  • Nuvation Showcases Four Engineering Reference Designs for the Video Security Industry
  • New 32-Tap Digital Potentiometer from Catalyst Semiconductor Offers Simple Up/Down Control for Easy Digital Interface
  • PMC-Sierra Appoints President and Chief Executive Officer
  • Chartered Extends Technology Development Collaboration with IBM to 22-Nanometer Process Node
  • New Intel(R) Centrino(R) Atom(TM) Processor Technology Ushers in 'Best Internet Experience in Your Pocket'
  • Xilinx Ships Virtex-5 FXT FPGAs, Delivering the Ultimate in System Integration for Designs That Demand High-Performance Processing and High-Speed Serial I/O
  • ARC and Toshiba Extend Collaboration to Develop Next Generation Multicore Configurable Processor Technology
  • Proven Software Solutions launches the Element Control Software Platform for managing network elements
  • Toshiba Offers a Wide Range of Embedded and Removable Memory to Address Growing Use of NAND Flash in Mobile Handsets
  • VPT Introduces More Than 50 New DC-DC Converter Modules for Use in Space Power Systems
  • NextWave Wireless Launches 'No Compromise' Second-Generation Mobile WiMAX Chipset
  • Mellanox Delivers First 40Gb/s InfiniBand Adapters
  • Toshiba MDDI LCD Controller Brings High-Resolution Video to Portable Consumer Electronics Devices
  • ANADIGICS Announces New Power Amplifier for AWS and KPCS CDMA/EVDO Mobile Equipment
  • Toshiba Brings New Image Sensors and Camera Modules to Mobile Handset Market
  • Magnum Semiconductor Licenses Sidense's Logic Non-Volatile Memory for Consumer Entertainment Products
  • New Infineon LDMOS RF Power Transistors Target 2.5 to 2.7 GHz WiMAX, Wireless Broadband Applications With Industry-Best Peak Output Power
  • PulseWave RF Announces Sample Availability Dates for Two New Wireless Base Station Digital Power Amplifier Modules
  • Aptina Imaging Introduces New Image Sensor for Security and Surveillance Cameras
  • Toshiba Satellite L350 Series Brings Affordability to the 17.1-Inch Laptop Form Factor
  • Beceem Introduces World's First Single-Chip, 65 Nanometer Mobile WiMAX Solution - Sets New Standard for Low Power Consumption
  • Quickoffice and ARM Partner To Provide Superior Mobile Viewing Technology
  • Toshiba Offers Affordable 15.4-Inch Satellite Laptops Starting under $600
  • MIPS Technologies Unveils Industry's First Multi-threaded, Multiprocessor IP Core for the Embedded Market
  • Motorola Launches the W24 Wireless Module Adding a Wi-Fi Technology to the M2M Module Family
  • 45th Design Automation Conference to Feature Diverse Keynote Lineup
  • Fujitsu Introduces 65-Nanometer 10G SerDes from Prism Circuits
  • Maxim's High-Performance and Highly Versatile Triple Controller Offers Sequencing and Tracking Control for Networks, Servers, and Telecom Applications
  • Imperas to Demonstrate OVP During This Week's Multicore Expo
  • Mobilygen Announces Industry's First Digital Video Recorder Design With High Definition Monitoring
  • TI introduces industry's first 16-bit, dual-channel DAC family with 1 Gbps LVDS inputs
  • Pericom Expands PCIe Offering With Industry First One Chip PCIe to UART 'Serial Bridge' Family
  • Sigma's Media Processor Is Selected to Power the Comcast/Panasonic Unique AnyPlay(TM) Portable DVR
  • Enpirion DC-DC Converter Quiets the Competition with its Low Noise
  • New Cypress Website Helps Designers To Reduce Electro-Magnetic Interference With Spread Spectrum Timing Solutions
  • Video: Texas Instruments Introduces Industry's First Single Chip to Integrate GPS, Bluetooth(R) and FM Technology
  • Texas Instruments announces industry's first multi-carrier, multi-standard development platform for wireless infrastructure base stations
  • LSI Introduces Industry's First Single-Chip, Low-Cost Solution for Content Inspection
  • Tekmos Introduces 'Drop in Replacement' for NXP P89C668 With the TK89C668 MCU
  • Chartered Completes Acquisition of Eight-Inch Wafer Fab Operation in Singapore
  • February Semiconductor Sales Show Modest Year-on-Year Gain
  • ON Semiconductor Launches Next Generation Audio Processor for Portable Communication Devices
  • PMC-Sierra Introduces Industry's First 10G EPON Reference Designs for FTTH Deployments
  • National Semiconductor Introduces Industry's First High-Current Flash LED Driver With Adjustable Over-Voltage Protection for Single or Dual LED Operation in Handheld Devices
  • Numonyx(TM) Enters Memory Market in a Strong Position
  • STMicroelectronics, Intel and Francisco Partners Close
    Transaction to Create Numonyx
  • Alltera's 2007 Annual Report Now Available

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    -- Jack Horgan, EDACafe.com Contributing Editor.

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