February 25, 2008
First 4 weeks of Shock & Awe then DVCon
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* Two weeks ago: News spread like wildfire that
EDN had laid off distinguished Senior Editor Mike Santarini, as well as Editorial Director Maury Wright. Even those who thought they understood the depths of the financial despair into which EDA ad dollars, and journalism, had fallen were caught by surprise.
* One week ago: Mentor announced estimates of $860 million in revenue for 2008, “stepped up cost controls,” and 5%-to-10% growth for 2009. Mentor stock rose 21% on the news. Synopsys announced Q1’08 revenues of $315 million, higher than the $313 million anticipated and a 2x increase in profits compared to the same period last year. At first blush, Synopsys stock rose 6% on the news. Cadence announced a $500 million stock repurchase plan. Cadence stock went up 5% on the news.
* Late last week: Cadence announced it will no longer exhibit at the
Design Automation Conference. Per the Press Release: “DAC provides the whole industry with an opportunity to come together to discuss technical challenges and solutions. We appreciate and will continue to fully participate in this aspect of the show. We do not, however, see similar value or ROI on the sales booth aspect. Our
CDNLive! series of global events provides us with a stronger, sounder platform upon which to engage more deeply with customers and partners.”
And then there was DVCon
DVCon – Verification, Low Power, and Parallelism in the Real World
DVCon is about real-world engineering. Period. It’s not about fancy, schmancy academics. It’s not about huge, over-produced marketing hype. It’s about designers learning what their tool vendors are doing, and vice versa. There’s just one real keynote, everybody gets lunch courtesy of the sponsors, and everything’s either on the first floor of the DoubleTree Hotel in San Jose, or just up the stairs on the second.
Nobody feels like they need to be in two places at once at DVCon. There are, at most, only 2 technical tracks underway at any one time, and presenters have a full 30 minutes to talk and then answer questions. The exhibit hall is only open from 4:30 PM to 7:30 PM,
after the last sessions of the day wrap up, and is always served up with beer and wine. Better yet, the exhibit hall is on a human scale – more science fair than vendor fair – and full of people who either already know each other, or want to get to know each and/or what the vendors’ tools can do.
The bottom line is, people actually learn things at DVCon – in particular, this year, about low-power design and formal verification – and then take that learning back to their place of work to share with others. It’s hard not to like DVCon.
* The Role of DVCon: As the sun rose over San Jose on the first day of DVCon, I shared breakfast with Conference Chair
Steve Bailey from Mentor Graphics, Program Chair
Tom Fitzpatrick, also from Mentor, Program Vice Chair
Ambar Sarkar from Paradigm Works, Past DVCon Chair
Gabe Moretti of
EDA Design Line and
DACeZine fame, and Publicity Co-Chair
Wendy Truax from HighPointe Communications.
The committee expressed their gratitude to conference organizers MP Associates, and to all of the sponsors: Accellera, Cadence, Jasper, Mentor Graphics, Synopsys, nSys, Certess, OVM, and OSCI & Friends (including ARM, Cadence, CoWare, Doulos, ESLX, Forte, JEDA, Mentor, and Synopsys). They also spoke to the roll DVCon plays in the annual cycle of technical conferences for the design automation industry.
Steve said DVCon’s known as a gathering place for working engineers, that over 700 people were expected at the conference this year, and the number of exhibitors was up (35 booths, by my count). Tom said the value of the conference is proven by word of mouth as much as by anything, because the quality of the papers is consistently good and engineers know DVCon is a place to learn and network. Ambar said the selection of those papers is taken very seriously, and always done with the tool users in mind. Steve reminded me that the authors retain the copyright for their papers, which is particularly appealing to presenters. Ambar, Tom, and Steve all commented on the success of the
sponsored tutorials on opening day, and said the session on new research drivers was a welcome addition to the conference. (Speakers at that session came from DEIS Universitá di Bologna and the Technical University of Braunschweig, putting to rest the idea that academics weren’t welcome at DVCon.)
Before the breakfast group rushed off to the Opening Session, I asked for advice on what to look for at DVCon 2008. Tom said to anticipate many discussions on different aspects of verification, assertion-based verification, in particular: “It’s no longer, Can you do assertion-based verification?’, but what is constrained random and why is it good.” Ambar said there would be lots of talk about low-power design and verification, and Steve said it was interesting to note the number of new EDA startups in the area of verification. Hinting that standards and consortia are always a hot topic, Gabe Moretti said, “What I find remarkable is the acceptance by
the industry of OVM!”
* OVM & VMM at DVCon: So, what is OVM? It had a clear presence at DVCon – sponsoring a half-day tutorial on Tuesday, a booth on the exhibit hall floor, and a lunchtime panel discussion moderated by
Dave Maliniak on Thursday.
Well, per the organization’s own description, “OVM is the industry’s first, open, interoperable SystemVerilog verification methodology. Developed jointly by Mentor Graphics and Cadence [an effort that earned an IEC DesignVision award, as mentioned earlier], OVM provides a SystemVerilog class library, examples, development gridlines and other collateral that incorporate many years of verification experience from both companies to assist users in developing modular, reusable, transaction-level cover-driven testbenches.”
So, what’s not to like? It turns out that Synopsys donated a library of SystemVerilog assertion checkers to Accellera in 2006, checkers that come out of the Verification Methodology Manual (VMM) the company published jointly with ARM. Synopsys would like to see Accellera continue to pursue verification standards efforts along those lines, and so the beat goes on. [See
2006 article in
EDA Weekly for further detail.]
Given the recent dust-up in the low power world – the Cadence-sponsored CPF (Common Power Format) versus the Mentor/Magma/Synopsys-sponsored UPF (Unified Power Format) – it’s not surprising that a collective groan has been rattling around in the industry for sometime over the specter of more Us-versus-Them, now in the verification world. Hence it was noteworthy that in the midst of DVCon, Synopsys Director of Quality and Interoperability
Karen Bartleson, who has served for many years on the Accellera Board, issued this challenge in her blog:
More and more, users (customers) are demanding one standard verification library. As a result of this growing interest, Accellera will start investigating the feasibility of creating a single, SystemVerilog verification library. My company, Synopsys, is committed to support our customers’ interoperability requirements. We are ready to fully support an Accellera initiative, contributing our technology and expertise towards a single standard. Our initial technical analysis indicates that this can be accomplished in a reasonable amount of time, with a reasonable amount of effort.
As Accellera investigates the viability of a single standard, we welcome Cadence and Mentor to support our VMM. We will be happy to provide them access to our VMM base class library source code and resolve any licensing issues and objections they may have had in the past. I sincerely hope that Cadence and Mentor will cooperate in Accellera, preventing the infamous standards wars from recurring. This is a golden opportunity for EDA companies to work together, diminish the “war” that has been brewing, and serve our customers at large.
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-- Peggy Aycinena, EDACafe.com Contributing Editor.