January 28, 2008
Fireside Chat: Rick Lucier & Jim McCanny
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Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

* Infiniscale SA announced a distribution agreement with
IVIS Co. Ltd., a Japanese distributor for EDA products. Per the Press Release: “IVIS was chosen on its reputation for building strong customer relationships and delivering compelling new EDA tools to the Japanese market.”

* IPextreme announced that “select IP cores are now available for purchase through the new online marketplace, the Core Store … Core Store products come fully packaged in an easy-to-use encrypted format with support available as an optional purchase item.”

* IPextreme also announced the appointment of
Kazuhiro Ogawa as President of IPextreme Japan. Ogawa has 28 year’s experience in high tech, working at Tokyo Electron Ltd., Fluent Inc., and Nihon Synopsys Co. Ltd.

* JEDA Technologies announced its NSCvCC code coverage product for C/C++ and SystemC designs, which the company says is intended for model developers, platform developers, system designers, and architects. Per the Press Release: “NSCvCC rapid code coverage checking helps to measure IP model quality and identifies code which has not been fully exercised in testing … NSCvCC measures the comprehensiveness of your verification suite, improving quality and productivity and reducing risk.”

* Magma Design Automation announced its Talus QDRC, which the company describes as “a physical design verification product that improves productivity and time to market for 65- and 45/40-nanometer designs by identifying and correcting design rule violations during implementation … Talus QDRC decreases overall design costs by addressing DRC problems before they delay design tapeout.”

* Mentor Graphics announced new technology in its Olympus-SoC P&R product that the company says will accelerate signal integrity closure and improve manufactured silicon reliability. Per the Press Release: “The Multi-Corner, Multi-Mode (MCMM) capability of Olympus’ Static Timing Analysis (STA) engine concurrently computes delay shift and glitch for any number of mode/corner scenarios in a single pass. MCMM analysis [addresses] reliability issues such as crosstalk delay, glitch, power, and electromigration while reducing the time to achieve design closure. The Olympus-SoC product’s detailed routing and optimization engines
have been enhanced to help eliminate SI violations concurrently over all variation scenarios.”

* Mentor Graphics also announced the third generation of its TestBench Xpress, which the company says “eliminates the traditional barriers of adopting hardware in-circuit emulation for system-level integration. When used in conjunction with Mentor’s Veloce family of hardware assisted verification products, TBX provides a software based, cost-effective and efficient way to perform hardware-software co-verification for embedded systems.”

* Mentor Graphics also announced an extension to its ESL synthesis flow that the company says, “enables users to implement even higher performance DSP hardware than previously achievable with Catapult for
Xilinx devices … The result is designs that operate 50-80 percent faster than results previously achieved by any high level synthesis tool.”

* Mentor Graphics announced, as well, that
Fujitsu Ltd. has added Catapult C to its standard ASIC design kit. Per the Press Release: “A number of ESL synthesis tools were assessed in order to meet Fujitsu’s stringent requirements for quality standards.”

* MIPS Technologies announced that
Entropic Communication has licensed “the MIPS32 24Kc synthesizable processor core for its next-generation broadband and residential gateway applications.”

* Nangate and
Ponte Solutions announced “a tight product integration that will help customers deal with the impact of process variation and design for yield.”

* OCP-IP announced a new debug specification has gone to member review. Per the Press Release: “The specification details an approach to a standardized OCP-bus compliant debug interface. The debug solution, an optional OCP port, implements a debug interface socket that can be added to all cores and IP blocks. The specification supports a uniform method of on-chip system analysis and access to embedded information at the core, multi-core, and systems levels.”

* OneSpin Solutions GmbH announced its 360 EC-FPGA equivalence checker, which the company calls “the industry’s first sequential equivalence checking solution dedicated to and priced for the FPGA market … Formerly an extension of OneSpin’s established 360 EC-ASIC equivalence checker, 360 EC-FPGA now is packaged stand-alone and priced for broad application in the FPGA market. OneSpin also has extended 360 EC-FPGA’s support to include all Altera Stratix and Cyclone FPGAs, and HardCopy; most Xilinx Spartan and Virtex products; and the Synplicity Synplify Pro synthesis flow – including gated-clock conversion.”

* OneSpin Solutions also announced the addition of a standard assertion language link to its 360 Module Verifier solution. Per the Press Release: “The link opens an additional gateway to complete, gap-free functional verification for companies invested in assertion-based verification (ABV) … Using 360 MV, they can exhaustively check and debug both existing and new SystemVerilog Assertions and Open Verification Library assertions. [Among new features]: Assertions can be written in-line or in a separate file and linked to the design-under-verification by means of “bind” statements. This allows users to either instrument the
RTL code or write additional assertions files to capture and verify DUV functionality, and integration conditions.”

* Ponte Solutions announced an updated version of the company’s YA System, version 0801, which the company says includes new defect analysis capabilities and enhanced features. Per the Press Release: “This new YA release can now analyze butted contacts, diffusion contact to gate shorts, source-drain shorts, and isolated contacts and vias. In addition, Ponte has enhanced the ease of use for its embedded memory analysis capabilities.”

* Real Intent, Inc. announced today that
Carol Hallett has been named Vice President of Worldwide Sales. Prior to joining Real Intent, she was Vice President of North American Sales at Tharas Systems, which was acquired by EVE.

* Sagantec announced it has “enabled
MathStar, Inc. to successfully port and optimize its high-performance Field Programmable Object Arrays (FPOAs) that perform at clock rates up to 1 GHz … Using Sagantec tools, Mathstar reused its 0.13um production-proven FPOA design and significantly shortened its new 90-nanometer technology implementation.”

* Silicon Canvas and
Synopsys announced the integration of Silicon Canvas' Laker schematic capture and layout environment with Synopsys' Hercules Physical Verification Suite (PVS). Per the Press Release: “Customers using Laker and Hercules PVS can now seamlessly navigate and view the design and electrical rule checks (DRC, ERC) and layout versus schematic (LVS) errors using Hercules VUE with the Laker environment.”

* Simucad Design Automation announced that
Elpida Memory Inc. has standardized on Simucad’s SmartSpice for analog simulation.

* Stratosphere Solutions Inc. announced that
Stone Pillar Technologies, Inc. has become as a member of its ICTrust Partnership Program. Per the Press Release: “Under terms of the partnership agreement, the companies have integrated Stone Pillar’s TestChipBuilder with Stratosphere Solutions’ StratoPro silicon IP platform to improve parametric yield at 45 nanometers and below.”

* Synplicity announced that Synplify Premier release 9.0, which the company says has been “optimized for Xilinx Virtex-5 FPGAs … This latest release extends the graph-based physical synthesis technology which has been implemented for
Xilinx Spartan-3, Virtex-II Pro and Virtex-4 FPGAs for more than two years. Synplicity also announced it has extended these benefits to FPGA designers targeting
Altera Stratix-III, Stratix-II and Stratix-II GX FPGAs, through the company's Synplify Premier Beta Program.”

* Synopsys announced “the qualification and immediate availability of the Synopsys Star-RCXT parasitic extraction solution for TSMC's 45-nanometer process technology. Per the Press Release: “Altera is now deploying Synopsys' Star-RCXT as the preferred extraction tool for its 45-nm design sign-off flow.”

* Synopsys also announced that IC Compiler was used in a 45-nanometer SoC device from
Matsushita Electric Industrial Co., Ltd., and is entering volume production. In addition, Matsushita used Synopsys' Design Compiler for RTL synthesis, and PrimeTime SI timing analysis solution and Star-RCXT extraction tool for silicon-accurate sign-off.

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-- Peggy Aycinena, EDACafe.com Contributing Editor.


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