November 19, 2007
Can One of the Big Three Compete in a Market Dominated by Others?
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor


by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


As proud as we are in the progress we have had in synthesis, more than 1,000 companies using us is a vote of confidence, the work is not done yet. There is a lot of development that needs to be done to catch up with advancements in the silicon. When we asked our customers we found three major challenges that typical FPGA designers are facing. The first one is in order to get timing closure there are too many iterations. The second challenge is that each iteration takes a very long time. It sometimes takes a day for just one iteration. The third challenge is how to make sure that the resources inside the silicon are utilized to the maximum because inside advanced FPGAs today there are
hard macros, all kinds of special purpose blocks. These are the three challenges that our customers told us need to be addressed.


How does your new product address these issues?

We have introduced a new product called Precision RTL Plus. The official announcement was September 24th. The product is shipping. This is a vendor independent solution for break through productivity. If you want to achieve your timing faster and predictably, it is about how to make you more productive. It has three breakthrough capabilities. It is easy to use for every designer and equally powerful for the vendor FPGAs. They are breakthroughs because none of them are me too. Each one of them has uniqueness and has measurable value to the end user. The first problem was there were too many iterations. For that we are introducing unique physical synthesis in order to minimize and shorten
the iterations. In order to reduce the length of the iterations, we have introduced the first technology for automatic incremental physical synthesis. In order to solve the efficient challenge of the architectural blocks we have introduced patent pending resource management equality.


We call the first breakthrough physically aware synthesis but it is really physical synthesis. It is the only multi-vendor physical synthesis. Let me break that down for you. Physical synthesis is now a reality and it must have features for all synthesis today. The reason is that much of the delay typically is no longer the cell but the routing length and the net delay. In order to solve the net delays, you need to have physical synthesis capability in your tool.


If you want a tool that is vendor independent, clearly the important capability of physical synthesis needs to support all the vendors because it is that central, that important. If the physical synthesis supports only one vendor, you will not be able to use the capability when you want to switch to another vendor. As obvious as this is, this is the only product that is true multi-vendor synthesis. Therefore we can confidently claim that Mentor is now the leading vendor independent tool. From another perspective it means 10% improvement in Fmax with a typical improvement of 5% to 45%.


What is the benefit of this Fmax improvement to the end user?

There are two major challenges. The first is timing and second is area. A third one we are now seeing is power. For many complex designs the requirement to achieve a certain clock speed is the number one challenge in design constraint. If you have a push-button like you have with this capability that can achieve an additional speed up of the clock by 10%, it can sometimes be the difference of meeting you design goals or not. Sometimes it can mean being able to change to a cheaper or less expensive device.


The average we and our customer have been observing with objective test runs is typically between 5% and 40% improvement.


What is innovative about this? Everyone understands that in order to have vendor independence, the physical synthesis needs to support all vendors. But up to now, no one could achieve that because whenever you have physical synthesis, it has to know the intimate details of the physical characteristics of the silicon. Therefore every additional vendor or every additional device was a major, major project. The innovation here is that we are now introducing a technology where it is easy to add new devices and vendors. Therefore, we are currently the only one. Just for comparison the only other physical synthesis tool which is available on the market supports only one of the vendors.
Synplicity has physical synthesis, Premier, for a year and a half but it still supports new devices only within Xilinx. We are support the four major vendors, 19 devices families.


What percent of the total number of FPGA devices does this represent?

When it comes to complex designs and the most common designs, I would estimate it would be 70% to 80%. There are hundreds of devices but when you look at complex designs and where designs are being focused these days, these 19 families are really covering the majority of designs,


When Xilinx, Altera, … introduces a new FPGA does Mentor have to come out with new models, update the software, …? How does that work?

We are very good partners with all of the vendors. When the vendor is in the initial stages of developing a new part, they disclose to us the details so when they are developing and readying the silicon, we are readying the software even before the silicon is available, long before. When the product is announced we are ready to support it. For every device that is being added, the synthesis tool needs to do something about it.


With physical synthesis we are reducing the number of iterations because you can get to your Fmax goals and time closure faster but you still need to iterate. Because most designs today are complex and challenging, iterations which include synthesis and place and route can take 8 hours, 10 hours. It is not unheard of to run over night. Therefore as you come closer to the end of the design and there is a change request or I need to change an inverter, then going through these 8 hours is very painful. For the first time Precision RTL Plus includes automatic incremental synthesis. This product also supports the traditional partition based approach. We are not just inventing a new way we
are supporting the previous way to handle incremental design.


Up to now if I made a small change and I did not want to wait for synthesis and P&R then to shorten the time the designer had to partition the design. This approach could be effective for team based design but in the vast majority of designs this turned out to be too complex. Therefore the designer community did not do that. For the first time we came up automatic meaning that the designer does not need to do anything in order to benefit from the shortening of the run time. There is up to 60% synthesis runtime saving. The nice thing about this is number one you do not have to do anything. You run it the first time to establish the base line. The next time you run assuming the change is relatively small, the synthesis will be smart enough to synthesize only the difference. Not only did the designer not have to do anything to benefit from the time saving, you are not compromising any quality of results. In the previous means of partition based not only was it complex and therefore most people do not do that but if you did partition it, many times you would end up with shortened run time but your Fmax or area would suffer. You would compromise the quality of results. The first automatic incremental synthesis does not require any partitioning or any preparation. You do not lose any QoR. Just like the physical synthesis where we support a broad range of devices and
vendors, all of the FPGA devices we support are enjoying automatic incremental synthesis.


When you combine the unique automatic incremental synthesis with Xilinx SmartDrive for the first time you have a complete incremental flow because synthesis is only one part, the other part is place and route. If you combine incremental P&R with Xilinx SmartDrive then for the first time you do not have to do anything especially in the late design stages you have an extensive shortening of the iteration.


For example if synthesis and P&R takes 10 hours, with this flow if you had a reasonably small change it would take one or two hours. This is a big difference. For the first time you have a complete incremental flow.


In these days it is quite commonplace to do partitioning. When you do that you are saving both in synthesis run time and the P&R runtime. Of course you have to make the effort of partitioning and need tool support as well. We have innovation here because sometimes the partition can be very big. If you do a small change within a big partition, all the others would re-synthesize the whole partition. Thanks to our incremental capability we will synthesize only the subset of the partition that is needed. We believe that up to now we are the only one with physical synthesis that support
multi-vendor and the only one with automatic incremental synthesis which is also vendor independent.


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-- Jack Horgan, EDACafe.com Contributing Editor.


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