October 08, 2007
Cappuccino & Creativity: Sangiovanni-Vincentelli, Sentovich, and Szymanski
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* eSOL announced that its eT-Kernel Multi-Core Edition RTOS suites are now available for
NEC Electronics’ NaviEngine system LSI chip for automotive navigation systems. In related news, eSOL also announced an agreement with
ARM to support ARM’s new Cortex-A9 MPCore multi-core processor with eSOL’s eT-Kernel Multi-Core Edition RTOS.
* Extreme DA announced the company’s GoldTime timing analyzer has been selected as the reference tool for STARC’s SSTA flow, v1.5.
STARC says it expects to release the v1.5 flow to its member companies shortly.
* Hantro announced that
Atmel Corp. licensed the Hantro’s new 8170 multi-format video decoder RTL. Atmel says it will “integrate the decoder alongside an ARM9 processor core in a chip targeted for multifunctional next-generation video devices such as personal media players and navigation systems.”
* Impinj announced that the company’s customers have shipped more than 600 million chips containing Impinj’s AEON NVM cores since 2003. That’s a lotta chips.
the specifications. Infineon’s implementations of MLI and MSC are also available from IPextreme as silicon-proven IP cores.”
Warren Savage is quoted: “Standards drive cost efficiency into markets by allowing interoperability between suppliers and providing customers with choices. We are excited to be able to provide these technological advances to automotive semiconductor suppliers all over the world.” Please note that Warren Savage is currently writing a blog about true SystemVerilog interoperability. It’s recommended that you go out and read his thoughts on the IPExtreme website.
* Jasper Design Automation announced GamePlan Verification Planner version 1.2, which the company describes as “a powerful tool for generating and tracking verification plans. [Version 1.2] includes the ability to import verification results, [and] delivers improved search capabilities, active hyperlinks in analysis views for easy organization, and a new Undo/Redo feature for improved usability.”
Jasper’s GamePlan Product Manager
Jay Littlefield, is quoted: "Since verification plan data and tracked results are stored together in an open XML format, users can now easily extract custom data sets for analysis, in addition to generating GamePlan's powerful standard reports. The flexibility of GamePlan provides a means to integrate disparate technologies, such as formal and simulation, into a single cohesive verification effort."
* In related news,
Jasper Design Automation also announced JasperGold Verification System v4.5, which the company says “delivers support for liveness properties, enhanced engine performance and support for properties containing multiple clocks, and includes improved initialization performance for easier formal analysis and automatic property grouping for faster proofs.”
Jasper VP of Marketing,
Craig Cochran, is quoted: "With its liveness property support, greater performance and powerful new modeling features, JasperGold v4.5 delivers sophisticated formal verification capabilities while minimizing the effort to attain high-leverage results. These new capabilities have been driven by real-world deployment within our customers' verification environments, in turn propelling the company's methodology and technology development to make Jasper the leader in successful deployment of formal verification."
* The MathWorks announced Embedded MATLAB, which the company says “enables MATLAB users to generate highly efficient, embeddable C code directly from MATLAB programs, avoiding the common, time-consuming and error-prone process of rewriting MATLAB algorithms in C Embedded MATLAB supports many high-level MATLAB language features, such as multidimensional arrays, real and complex numbers, structures, flow control, and subscripting The conversion to C code is performed by Real-Time Workshop, [which] automatically produces embedded C that is comparable to hand coding in size, performance, and memory use.”
Matt Schurman, CTO at GlucoLight, offered testimonial in the Press Release: “By introducing the Embedded MATLAB language subset and Simulink in our design process, we virtually eliminated the errors previously experienced with manual code translation from MATLAB to C. At the same time we shortened the development of subsequent product generations - from design all the way to implementation”
efficiently, test patterns can be smaller and more highly compressed.”
efficiently processing late cycle design changes; and (3) a unique resource management technology for optimized design performance.” Testimonials were provided in the Press Release from Altera,
* MIPS Technologies announced that the Hong Kong Applied Science and Technology Research Institute has licensed MIPS’ low-power MIPS32 M4K processor core “for the development of advanced H.264 video processing applications.”
Raymond Chiu, VP at ASTRI, is quoted in the Press Release: “With the emergence of H.264 as the preferred standard for high-quality media distribution and compression, our customers require video processing solutions that offer lower power consumption and system costs without sacrificing performance. Leveraging MIPS’ commanding presence in digital consumer applications and the area and power efficiency of the powerful M4K core enables us to deliver innovative designs that shorten production cycles and accelerate time-to-market.”
Relevant to the announcement, I had a lengthy phone call with Pyxis CEO
Phil Bishop and company VP of Marketing
Mitch Heins. Bishop said, “The existing industry approach to DFM is layered, iterative, and includes antiquated flows. There’s just not enough manufacturing data or runtime data in those flows. What differentiates Pyxis from other DFM-oriented players is that we’re about implementation. We’ve actually embedded the [crucial] embedded analysis [data] into our router.”
Mitch Heins added, “We’ve taken a fresh approach to attaching the DFM problem. We don’t necessarily believe that smaller and tighter [design rules] are better. The other guys are bolting DFM solutions onto [their existing flows], but that’s like putting wings on a bus. It won’t be optimal no matter how it works. We’re about a correct-by construction approach. We’re not just working to optimize timing or area, but also working to optimize manufacturability and yield-aware routing while we’re doing it.”
Phil said, “Other DFM players are doing routing layer by layer. Pyxis, on the other hand, does 3D wire balancing, optimizing across those layers. The big difference is in the concurrency with which we do the layout. [In particular], we have 34 different DFM rules, which makes for a more optimized layout. And, we’re working closely with
PDF Solutions and
Brian [recently acquired by ASML] to improve the process. [And while] Pyxis is definitely a products company, we also have a service offering that is allowing us to [demonstrate the solution] to our customers.”
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-- Peggy Aycinena, EDACafe.com Contributing Editor.
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