October 01, 2007
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

The top articles over the last two weeks as determined by the number of readers were:

Microsoft and Cadence to Cross-License Patent Portfolios Microsoft Corp. and Cadence Design Systems Inc. have entered a patent cross- licensing agreement, expanding on a long-standing relationship between the two companies. The agreement allows broad access to each company's respective patent portfolios to facilitate future technical collaboration in areas of common interest to both companies.

Since 2003, when Microsoft announced it was "open for business" on IP, Microsoft has continued to license its IP portfolio, providing access to the fruits of its significant R&D efforts. The company maintains a growing worldwide quality patent portfolio that includes several thousand issued and pending U.S. patents. Recent Microsoft cross-licensing collaborations include Cisco Systems Inc., LG Electronics, Samsung Electronics Co. Ltd., NEC Corp., Seiko Epson Corp., Siemens AG, SAP AG and Toshiba Corp.

Berkeley Design Automation Selected by Matsushita Electric Industrial Co., Ltd. for Digital-RF Chip Design Platform Berkeley Design Automation, Inc., provider of Precision Circuit Analysis technology for advanced analog and RF integrated circuits, announced that Matsushita Electric Industrial Co., Ltd. has entered into a partnership for analog/RF and mixed-signal design verification for Matsushita's Digital-RF Chip Design Platform. The partnership is based on the technology from Berkeley Design Automation's Analog FastSPICE and RF FastSPICE tools which provide full SPICE accuracy,
with 5x-10x faster speed and 5x-10x higher effective capacity than traditional circuit and RF simulation. Matsushita's design teams will use this capability to further its lead in complex digital-RF ICs for mobile communications and digital TV.

Mentor Graphics Accelerates FPGA / PCB Design Collaboration with New I/O Designer Product Targeted at PADS Users Mentor announced the availability of the PADS I/O Designer product specifically targeted at its PADS product user community. For designers implementing complex FPGAs on their PCBs, the I/O Designer product has a proven track record of decreasing design cycle time, improving performance, and lowering product costs. These same benefits are now available to the PADS product users at an aggressive entry price as the use of high density, high performance FPGAs increases across
the spectrum of electronic products. For the first time the PADS I/O Designer product is being made available to the PADS community.

Ciranova Appoints Eric Filseth as CEO Ciranova, Inc., an EDA start-up developing open and robust automated layout technology for analog and custom integrated circuit design, announced that Eric Filseth has been appointed chief executive officer. Filseth spent a total of 17 years with Cadence Design Systems, where he was most recently marketing vice president for Digital Implementation products. He also held executive positions with Silicon Perspective Corporation and Sente, Inc. Previously, he managed product marketing for analog, RF and mixed-signal products at Cadence. He started
his career in 1983 as an analog design engineer with National Semiconductor. Filseth received an MBA from UCLA and a BSEE from Stanford University.

Nikon and Synopsys Announce Manufacturing-Aware DFM Solution for 45 nm and Below Nikon Corporation, a lsupplier of lithography equipment for microelectronics manufacturing, and Synopsys announced that Nikon's proprietary optical lithography exposure tool data is available for the latest release of the Synopsys Proteus optical proximity correction (OPC) software. As part of an ongoing collaboration, the two companies developed an embedded scanner parameter module, which delivers the "manufacturing-aware" OPC and resolution enhancement technology (RET) lithography simulation models
needed for advanced 45-nanometer (nm) and below IC (integrated circuit) manufacturing. Mutual customers can benefit from improved OPC model accuracy and reduced time to silicon.

Other EDA News

  • Other IP & SoC News

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    -- Jack Horgan, EDACafe.com Contributing Editor.


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