October 01, 2007
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Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Editor: At time of its introduction by ClearShape InShape pricing started at $300,000 per master license per year. Distributed Processing was also available at incremental pricing. The same price was given for OutPerform.

When the technolgy identifies hot spots how is that information fed back to the designer?

Good question. Let’s step back to the design tools that can read that information in from a file that is called hot spot interface format (HIF). This file format has two elements to it: the x,y location of the hot spots and a hint as to how to fix that hot spot. You move this wire 3 nm west and this wire another 2 nm to fix this hot spot. It gives a series of hints. Those hints and hot spot locations go to our nanoroute technology which will correct for the hot spots as well as the Cadence Chip Optimizer which also corrects for them.

If this techncology is to work not only with Cadence RET/OPC tools but other vendors’ OPC tools, don’t you have to know something about how each such tool operates?

The strategy even prior to the acqusition by Cadence was to be RET/OPC agnostic. The approach they have taken is to work with the foundries to develop test chips. They have proprietary algorithms that do not just model the litho effects but the whole transformation from the original ideal layout structure which looks like a bunch of rectangles to what actually gets printed on silicon and read through sen images as contours. They have built some pretty heavy duty math that takes the transformation between all those different scenarios of patterns in GDS II and the corresponding patterns that come through on silicon. They do not need to model or comprehend the specific OPC tools.
They take into account a lot of other things beyond OPC like biasing and retargeting, things that go on from the time the layout is accepted by the foundry until the time when those patterns are printed onto silicon. They model that whole process. The advantage of this approach is first off it is very, very fast. It is also quite accurate.

TSMC went through a process over the last year and a half of qualifying different litho tools or litho analysis tools on the design side to determine which tool would be what they call the litho process checker, the LPC. They asked customers to run an LPC tool before taping out so that they would know that they are getting litho clean designs. The first product to be qualified at 65 nm, 55 nm and 45 nm and until recently the only product that was qualified was ClearShape. It was way ahead of anybody else. It sort of speaks to the level of accuracy provided. They also provide much better speed than competing technology because they take their OPC tool and repurpose it for the design
side. It can take one to two weeks to run a litho check on the design side which is impractical for designers. They need an overnight run type of tool.

How big a company was CleaShape when Cadence acquired it?

They were in the 30 to 40 person range.

How much did Cadence pay for ClearShape.

I’m sorry. We are not disclosing that information.

What did Cadence recently announce at CDNLive?

We announced a design flow RTL to GDSII targeted at the most advanced processes, 65 nm and 45 nm. The purpose of this design flow is to really enable custmers to account for the variability in design at these advanced process nodes, to bring the knowledge of manufacturing effects to the designer so that they can tape out knowing they are going to get a yield without over guard-banding. Before this technology was available, the approach most people would take is to just guard-banding. The big manufacturing effects were litho and CMP. Doing that guard-banding makes it more difficult to achieve timing, to meet your power and area requirements and to close your design. It impacts
every axis of the design, if you have to add too much guard-band. It allows designers to take away all that excessive guard-banding, model those manufacuring effects and understand where those effects impact what parts of the design and to compensate where you have to and don’t compensate where you do not have to. That’s the key is allowing the design to manage the variability of the design.

The way we do that is we provide these models with litho, CMP and random variation effects into the design. The approach we provide to the flow in three phases. There is a prevention approach where you try to prevent these manufacturing effects from getting into the design in the first place through automation. Then the analysis phase where we analyze the design for maufacturing effects like CMP and litho. And then there is optimization phase where you correct for the effects and optimize the design for yield.

As part of this flow we have introducted a number of new technologies. The first new technology is built into our existing Encounter nanorouter product. It is a fast litho estimator. Essential what it does is as the tool is routing it identifies patterns that are going to be hard to be printed by the manufacturer, those that are lithographicaly challenged. It manages to avoid those paticular routes. It will come up with alternate routes that will be clean from a litho perspective. This technology typically reduces the number of hot spots by as much as 60 percent to 80 percent right off the bat. It gets rid of the gross errors very quickly.

The next technology we introduced is a litho physical analyzer that was previously the InShape technology from ClearShape and then the Cadence Litho Electrical Analyzer which is the high performance technology. The difference between the two products is that the first one, the physical analyzer, is the one that looks at your design, it could be a custom block in Viruoso or it could be a full chip in Encounter, and it analyzes that design using the model that the foundry creates to identify what we call the litho hot spots and gives hints on how to correct those things. It then passes those to the optimization engine for correction. The other thing the physical analyzer does is it
creates contour of the actual structures. So if you lay down a wire, it actually shows you the curvey shape of the wire due to the litho effects. The Cadence Litho Electrical Analyzer has the technology to extract those contours and understand the impact of those countours on both timing and power. So you get more accurate power and timing analysis.

The third technology we are introducing is the Cadence CMP Predictor. This is a technology based on the Praesagus acquisiton about a year and a quarter ago. This predicts the thickness variability due to CMP effects and once again identifies hot spots in this case CMP hot spots where you have too much variability, too big hills and valleys in the design that could cause yield fallout. It also identifies the impact of that thickness variability on timing. It passes information to our extraction engine which extracts the thickness variability and applies that to timing.

The last technology that is part of this release is the Encounter Timing System GXL. Last year we introduced the Encounter Timing System which was our static timing analysis tool. That has done quite well in the marketplace. We are now introducing a new version, GXL, which is a high end version that does statistical timing analysis. The high level goal of that technology is not to require designers to run a number of corners where they do timing analysis of best case/worse case combinations of power, voltage, process and temperature and then look at litho, CMP and other sources of variability. The number of runs from the corner perspective is growing substantially. Rather than that
approach we take a statistical compliation of all these effects and apply that to one run that does the variability of timing and from that you can determine whether you can tape out.

There are variability effects due to lithography. A transistor that is drawn in the Cadence environment, the Virtuoso environment, and what actually gets fabricated is different. There is a signifcant amount of variability in how different those shapes look. You can have complete control of the process window but a transistor whose neighbors are different and there are some 40 different cases, has variability in its performance and timing. At one process window you can have up to 22% variability based just on the context of where that transistor sits relative to other transitors and up to 300% variability in leakage. That can be compounded by the fact
that the focus and exposure of your litho equipment can vary as well. So you can see a compounding of effects due to litho at 45 nm.

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-- Jack Horgan, EDACafe.com Contributing Editor.


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