September 10, 2007
September Uptick
Please note that contributed articles, blog entries, and comments posted on are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


Who says there’s no such thing as analog IP?

MIPS Technology is acquiring Portugal's
Chipidea Microelectronica SA, an analog IP company. The Press Release outlined the details: “Under the terms of the transaction, MIPS Technologies will pay an aggregate of $147 million in cash, with an additional performance-based milestone payment of 610,687 shares of MIPS Technologies' common stock in 2009. MIPS Technologies will make an initial payment of approximately $120 million [on August 27th] from its current cash reserves, with the balance released from escrow within two years subject to an indemnification holdback and deferred payments for the Chipidea co-founders remaining with the company.”

MIPS CEO & President
John Bourgoin sees synergy in the acquisition: “Analog represents an essential component of our IP growth strategy, and has become one of the key strategic considerations in customer designs today. Chipidea is the clear leader in analog IP with a broad product base, an impressive array of customers worldwide, and excellent financials. The synergies of MIPS Technologies and Chipidea are compelling for our customers' SoC design initiatives.”

Reflecting additional synergy,
Chipidea just announced that
Cadence Design Systems is licensing Chipidea's USB 2.0 OTG Link Controller and PHY for integration into Cadence’s newly announced SoC Functional Verification Kit (see below).


2008 Olympics as tech driver …

First, per the Press Release: “As the
Beijing 2008 Olympic Games are drawing near, more fabless and design companies are targeting the digital TV market. The research and development of relevant chips are advancing at an unprecedented speed. However, there is currently no uniform standards in low-power design, IP access, and foundry access for local manufacturers in the mobile TV market in China, making it tough when they want to compete in the market.”

Synopsys and
Semiconductor Manufacturing International Corp. (SMIC) have announced a “strategic alliance to develop a low-power design solution optimized for the mobile TV market in China, while also providing key IP components … the solution is based on 130-nanometer and 90-nanometer fab processes. In addition, the companies will provide key IP required by mobile TV IC designers … [The agreement] also calls for the provision of design and counseling service to help Chinese chip manufacturers take timely advantage of opportunities in the mobile TV market.”

Chi-Foon Chan, President and COO of Synopsys, is quoted: “It's our great honor to form this strategic alliance with SMIC to support Chinese chip manufacturers and the development of the digital TV market.”

Richard Chang, SMIC President and CEO, is also quoted: "Synopsys has a leading technology advantage in IP and low power design. I believe our cooperation will promote the development of China's digital TV sector's standards and marketplace."


Cadence – the WYDIWYG DFM flow

Though it may not be the most euphonic of names, Cadence’s new DFM initiative – What You Design is What You Get – is not out to win any word-smithing contest. It is, however, out to win one of the biggest prizes in EDA – dominant market share in the design-for-manufacturing world.

Monday, September 10th marks the opening day of CDNLive! in Silicon Valley, and it also marks the formal announcement date for WYDIWYG. I’m guessing that’s not a coincidence. If you’re at CDNLive!, you’ll hear all about it there. If you’re not, here’s a thumbnail sketch of the announcement, based on a phone call and PowerPoint presentation I shared with some of the folks from Cadence on August 31st.

Cadence VP
Eric Filseth acknowledged that any DFM flow is a complex one, with multiple targets – floorplanning, signal integrity, timing closure, IR drop, dynamic and passive power, ATPG coverage, and DFM closure, among others – and not necessarily in that order. He also said, at 65 and 45 nanometers, people are distressed that what they’ve designed is not necessarily what’s coming out of the fab, so they’re putting a lot of guardbanding into their designs. Too much guardbanding, which wastes money, time, real estate, and power. Now Cadence believes they’ve got the answer to all of this DFM “whack-a-mole” stuff (my phrase, not
Eric’s) and hence it’s here – the Cadence DFM flow.

WYDIWYG includes, per Slide #2 on the PowerPoint presentation: New design capabilities for 45 nanometers, accurate modeling of manufacturing effects within the design flow, prevention, analysis and optimization through physical design and signoff, new core technologies – patent-pending fast litho estimation and InShape/OutPerform litho physical and electrical variability analysis (courtesy of last month’s Cadence/Clear Shape acquisition) – plus a new CMP Predictor and Encounter Timing System GXL statistical timing analyzer.

In a nutshell, it’s a “model-based, variation-aware solution” that’s heavily dependent – per
Deo, now at Cadence thanks to the Clear Shape acquisition – on the “deep relationships” that Cadence has built and continues to maintain with organizations such as IBM, TSMC, UMC, and so on. In other words, the people who can give Cadence the info and/or models they need to get the manufacturing-awareness back upstream into the hands of the designers.

Okay, so there are some of the words from the WYDIWYG phone call and PowerPoint presentation. Now the hard part begins.

Will the customers understand WYDIWYG, and will they “get it” in both senses of the word? Will they comprehend WYDIWYG? And, will they buy WYDIWYG?

Cadence clearly believes the answers to both questions will be yes.


Read any good books lately?

Okay, they’re not trashy novels, but you’re too cool for pulp fiction anyway:

* Understanding Fabless IC Technology – Straight from the
FSA (Fabless Semiconductor Association), this one sounds like it might be a keeper, even at $69.95. Elsiver’s the publisher and you’re probably the reader if you’re interested in 300+ pages discussing the number one business innovation in the semiconductor supply chain over the last 20 years – the fabless/foundry model. The FSA says the book is targeted at a wide audience – everybody from fabless employees, to IDMs, suppliers, investors, legislators, entrepreneurs, and college students – and “gives insight into the various aspects of the outsourced semiconductor supply chain, [describing] the interdependence semiconductor companies
have with these suppliers using the fabless business model. [It also] addresses questions on how fabless employees should handle various cultural, language and time zone differences, to ensure operational efficiency.”

I haven’t actually seen the book up close, but it was waved around in front of the audience at the August 21st FSA luncheon in Santa Clara, so I know it really exists. You can buy it on Amazon and you’ll get a discount if you’re an FSA member.

* SystemC Behavioral Synthesis Style Guide from
HD Lab, Inc. promises to be “a reference book that documents production-proven expertise and design techniques based on SystemC.” The company says the book captures its 3 years of experience in SystemC design, verification, and methodology consulting, and provides “well organized, easily implementable” suggestions for the reader. In fact, they’re so sure you’ll love this book, they’re suggesting that you’ll reduce design cycle time on projects with over 3 million gates by anywhere from 33-to-50 percent. Along with an intro to SystemC, the book includes coding suggestions for design reuse and behavioral synthesis examples using
Forte Design Systems’ Cynthesizer. You can get the book by interacting directly with HD Labs, but I’ll bet Forte can also help you out should you be looking to add this one to your library.

* Cellular Handset & Chip Markets '07 – It’s not cheap ($3750), but this one from
Forward Concepts promises to keep you up at night. It’s an “in-depth study” of the worldwide cellphone market and the chips that love them. If you order the study, you’ll get 370 pages, info on 100 companies, and “dozens of forecasts by technology and by region through 2011 of handsets, subscribers, and chips of all types. In addition, the report provides estimates of the market shares of cellphone vendors by air technology (GSM, GPRS, EDGE, CDMA2000 1xEV, 1xEV-DO, WCDMA, WEDGE, HSDPA and even PHS/PDC/iDEN/TDMA).” Can you hear me now?

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-- Peggy Aycinena, Contributing Editor.


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