August 27, 2007
Hot Chips, Cool Books, Brainiacs & Workaholics Abound
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor


by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


Naturally, Sun wanted us to know that their energy saving derives in part from a “technolgoy refresh” to the newest of Sun’s cool servers and cooler, denser chips. It also derives from aggressive evaluations of their global energy needs, and an open give and take with employees who have been willing to offer up cunning suggestions to cut back, reduce, condense, and even eliminate facilities outright if more optimal computational and data storage solutions can be found. Hence, Sun’s not only offering their hardware to the industry at this point, they’re also offering consulting services to help you and yours make your operations and facilities more
eco-responsible, as well.


Per the Press Release: “Sun's Eco Responsibility Initiative is guided by three principles: Innovate, Act and Share. Sun innovates by making products and services that are both good for the environment and good for business. Sun acts by operating in an open, eco-conscious way. Sun shares by making information and technology available to others so that we can all move forward and participate in an increasingly sustainable way.” Nice!


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Chapter 8: On the Road Again – Stuff to Do & See


Okay, enough about the past. Now it’s time to plan for the future …


Altium is holding a seminar road show in 16 cities across North America in the fall. Per the Press Release: “The sessions will unveil the powerful new features of Altium Designer and how they combine with Altium's Desktop NanoBoard reprogrammable development platform … Sessions will include a practical workshop to demonstrate the potential of FPGAs.” FPGA novice or expert, everybody’s invited.


ARM Developers’ Conference
comes to Silicon Valley October 2nd to 4th. ARM will undoubtedly have announcements at the show, plus there will be keynotes, food, booths, and all the other stuff that the EDA world knows and loves. You should plan on attending.


CDNLive! is Cadence Design Systems’ User Conference and it’s happening September 10th to 12th in Silicon Valley, and is part of the company’s global road show. Other mega-organizations providing sponsorship include ARM, IBM, TSMC, UMC, and the Common Platform group, among others.


EDA Tech Forum,
billed as “The Largest EDA Industry Event” and brought to you by Mentor Graphics and others including ARM, Altera, Lattice, and The MathWorks, announced keynote speakers for the September 12th event in Santa Clara. NASA’s Steve Squyres will present "The Spirit and Opportunity of Mars," and iSuppli’s Andrew Rassweiler will chat about "Apple iPhone - Design Choices and Comparative Analysis." They’re saying 4.5 million iPhones will ship this year. Do you have yours yet?


FSA is having their fall Suppliers Expo conference and networking event, also on September 12th in Silicon Valley. Expect booths, food, sessions, panels, and chotskies at this event, as well. Over 100 companies will be there. Will you be there, as well?


Novas Software announced its 2007 International User Conference, happening in a host of locations, will highlight "Enhancing Your Verification Productivity" with technical tutorials and case studies. If you’re in Shanghai, Beijing, Taipei, Hsinchu, Tokyo, Bangalore, Irvine, Austin, Santa Clara, Ottawa, Munich, or Bristol, you can catch the conference. Happily, “The conference agenda for each geographic region is customized to address the industry trends and specific interests of chip designers in US, Europe, and Asia. A major highlight for the U.S. and Asia programs is the tutorial – Getting the Most Out of SystemVerilog
– developed by renowned expert and industry consultant Cliff Cummings.


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Chapter 9: Calling all papers – DVCon & ISQED


DVCon 2008 – The 2008 Design and Verification Conference, sponsored by Accellera, is accepting paper, panel and tutorial submissions for DVCon 2008 (February 19-21, 2008 in San Jose). Appropriate topics? Low-power design and verification, formal verification, multi-clock verification, design and verification case studies, verification and design release management, functional coverage and verification data management, verification methodology and testbenches, and verification IP development. Proposals are due September 19, 2007


ISQED 2008 – The International Symposium on Quality Electronic Design (March 17-19, 2008, also in San Jose) is calling for papers in the following areas: manufacturing, semiconductor technology and devices; electronic design; and design automation and CAD. Proposals are due by September 30, 2007. Note that ISQED proceedings are published by IEEE and ACM.


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Chapter 10: MIT Rocks!


“A 5-member team from MIT took home the winner's cup in the 2nd annual HW/SW co-design contest sponsored by the ACM-IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007) held in June in Nice.”


“The challenge was to implement a high-performance matrix-matrix multiplication (MMM) using any hardware and software design methodology targeting any FPGA development platform. Contest organizers Forrest Brewer from U.C. Santa Barbara and James Hoe from Carnegie Mellon provided a software-only starter reference solution for the Xilinx XUP development board … Nine teams of U.S. and European university students started the contest, with only MIT and Virginia Tech submitting a final design.”


The MIT team included Nirav Dave, Kermin Fleming, Myron King, Michael Pellauer and Muralidaran Vijayaraghavan from MIT's Computer Science and Artificial Intelligence Lab (CSAIL). Not surprisingly, they completed their design using Bluespec’s ESL synthesis environment.


[Editor’s Note – As I’ve got a kid of my own laboring away in CSAIL at MIT, I’m distinctly jazzed about this particular news.]


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Chapter 11: Can you say the alphabet backwards?


Zuken is now offering “free simulation design kits to assist with the integration of Altera’s new Arria GX FPGAs onto PCBs. Per the Press Release: “Zuken is quick to provide users of its enterprise-wide advanced packaging and PCB design environment, CR-5000, with simulation design kits that enable rapid and easy adoption of the devices.”


Xilinx announced collaborations with three fairly well-known EDA companies to promote “ultra-high capacity” FPGA design verification. Xilinx engineers say they’ll work with folks from Cadence, Mentor Graphics, and Synopsys to “define and implement new verification flows to maximize productivity and quality of results for ultra high-density designs targeting today's 65-nanometer FPGAs as well as new and emerging FPGA architectures.“ Bruce Talley, VP of the Design Software Division at Xilinx, is pleased: "By collaborating with the industry's leading EDA providers, we can develop solutions to address the challenges faced by our
customers at 65 nanometers and beyond." Surely you’ll be hearing more about all of this going forward.


TEA Systems announced a new product that the company says “enhances the control of overlay and registration in advanced semiconductor manufacturing to minimize the influence on critical feature dimensions and yield. Vector Raptor is a seventh generation overlay control tool specifically designed to address the unique problems now being introduced by double patterning and sub-45-nanometer process-node technology …VR provides an object-oriented, fully-interactive graphic interface for advanced control of overlay/registration with matching to any format feature-profile or film data.”


Sonics announced the company’s Sonics SMART Interconnect solutions are available as library elements for Mentor Graphics' Vista and Visual Elite products. The companies say, “Mentor Graphics … now offers a complete configuration, analysis and verification of SystemC SoC platforms based on Sonics SMART Interconnect solutions … With this announcement, Mentor Graphics and Sonics are ensuring interoperability between Mentor's ESL design tools and the SystemC versions of Sonics SMART Interconnect solutions.”


Solido Design Automation has named Douglas Konkin Vice President of Product Development. Previously, he was Director of Software Development for fabless semiconductor company PMC-Sierra, managing the Saskatoon design center. Prior to PMC-Sierra he was VP of Technology at HyperCore Technology. Konkin has an M.Sc. In CS from the University of Saskatchewan and a B.Sc. in engineering physics from the Royal Military College in Ontario, Canada. He also served as a signal officer in the Canadian Army.


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-- Peggy Aycinena, EDACafe.com Contributing Editor.


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