August 27, 2007
Hot Chips, Cool Books, Brainiacs & Workaholics Abound
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor


by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


Meanwhile, Mentor Graphics thrilled fans, analysts, and investors with their Q2 earnings reported out on August 23rd – MENT shot up 18% on August 24th! With Q2 revenues coming in at $205 million, the numbers were up 15% over the same period last year, putting the company on track for an $820 million fiscal year in 2007.


Press Release quotes attributed to Mentor Chairman/CEO Walden Rhines were ecstatic: “During the quarter, we saw strength across all of our system-related product lines. In addition to strength in more traditional systems design segments like FPGA and PCB design, we also saw significant strength in automotive design and ESL products.”


Real-time soundbites from the conference call were equally exultant. Mentor President Greg Hinckley evoked Gary Smith and EDAC during the call to support the thesis that the EDA market is moving up and to the right and to insist that Mentor‘s contributing to that trend. In addition, Hinckley noted that anything that even “touches” system design is heavily in demand, and hence Mentor benefits because the company’s so heavily positioned in ESL. He also crowed, “Our RET business is booming. We’re well positioned in design for manufacturing!”


Rhines added to the optimism on the call by insisting that neither Mentor’s newly released Veloce product line, nor Mentor’s newly-acquired Sierra Design Automation Olympus technology, face any significant competition in a solutions-hungry marketplace.


Rhines also commented on the Mentor/Cadence OVM announcement : “We really don’t need 3 different verification methodologies in the industry. Mentor has been in the lead with our AVM technology. By joining with Cadence’s URM to create OVM, we’re providing what the industry wants, namely open standards and consolidation of industry resources around fewer standards.”


By the way, if you think there’s nothing substantive that takes place during an earnings call, I’d invite you to mosey on over to the Synopsys and/or Mentor websites to listen to these archived earnings calls. They’ll be available for a few more days and are actually quite instructional. If you do, see if you sense a greater willingness on the part of the analysts to grill Mentor executives on their numbers versus their treatment of Synopsys execs. Perhaps it’s just my imagination, but it sure seemed that way to me.


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Chapter 5: Hot Chips & Brainiacs – Cores & snores multiply like rabbits


There were over 600 hard-core chip design folks in and around Stanford’s Memorial Auditorium from August 19th to 21st attending the 19th annual edition of Hot Chips. Conference organizers told me it was the largest attendance since the bubble burst in 2000. I caught 4+ hours of the event on Monday, the 20th, and several more hours on the 21st.


Hot Chips is a single-track conference, so if you just plunk yourself down in the auditorium you’ll catch all the action. Among the speakers there, I heard 30-minute presentations from Erik Lindholm from NVIDIA talking about the GeForce 8800, John Nickolls, also from NVIDIA, talking about computing on GPUs, Prof. Wen-Mei Hwu from the University of Illinois talking about programming parallelism, Mike Mantor from AMD talking about the Radeon HD 2900 and graphics shader architecture, and Yatin Hoskote from Intel talking about a prototype processor with 80 cores. I also heard Verghese George from Intel talking about the 45-nanometer Penryn.


In all of these presentations, we were looking at detailed descriptions of chips that ranged from 550 to 700 million transistors, monsters with anywhere from 300 to over 2000 pins, performance metrics ranging from 575 GFlops/sec to upwards of a TeraFlop, dozens of on-chip GPUs, with and without CPUs, and mind-boggling numbers of available threads, anywhere from thousands to the tens of thousands. It’s technology that’s practically sci-fi in its scale and potential for computational and graphics-processing power.


Unfortunately it’s warm in Palo Alto at this time of year, so when you combine a packed auditorium, too-little air conditioning, too many laptops, and a big mid-day lunch, you often get a lot of snoozing across the room. That’s not to say the chips themselves aren’t hot, but engineering managers/technical session speakers aren’t always the most gifted when it comes to dramatics and oratory, so the splendor of what‘s been accomplished can be masked by a lack of flair and a lack of air. After the fact, however, when the oxygen’s flowing once again and you review your notes, these ginormous chips can be seen for what they are – truly astonishing


And distinctly underutilized.


Illinois’ Wen-Mei Hwu, the most dynamic of the speakers I heard at Hot Chips, nailed it when he said most programmers today only understand their portion of a larger application, so the algorithms need to be re-designed and the programmers re-trained to see the big picture and take advantage of all of the thousands of threads the hardware is offering.


Hwu’s research on a variety of applications, however, indicates it’s easier said than done to get software developers to fully appreciate and utilize the massive features being thrown their way. Optimizing shared resources, accessing local and global memories, and attending to what he describes as “real, but rare dependencies” are all part of the learning curve that software guys will have to surmount before the hardware realizes its full potential.


Standing amidst the brainiacs outside of MemAud during one of the coffee breaks, I heard one guy summarize the problem even more succinctly than Dr. Hwu, “The thing is,” he said to the guy standing next to him, “Programmers just really don’t know how to parallelize their programs. It’s as simple as that.”


So, clone away you clever cores, but know you’ll have to wait a spell before your dreams of grandeur come to fruition.


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Chapter 6: Stalled Industries – Glum Chums at FSA


Ten miles south of Palo Alto, it was all glumness and gloom at the FSA luncheon/panel discussion that took place in a remote corner of the ghostly, empty Santa Clara Convention Center on Tuesday, August 21st. What a relief to leave there, after what felt like a 2-hour wake for the fabless semiconductor industry, and return to the technical gravitas and intellectual oomph of the hundreds of real (albeit snoozing) engineers considering real technology back at Hot Chips that afternoon.


Don’t take my word, however, for the general tenor of the conversation at the FSA luncheon. You can read my version of the transcript posted to
EDA Confidential and see for yourself. The fact that panel moderator Brian Fuller, now working in PR, opened the panel discussion with the statement – “The industry is dead” – says it all. Although Fuller later told me he was simply attempting to jump-start the conversation by being provocative, nobody actually disputed his sentiment during the entirety of the 90-minute panel discussion that followed, short of one contrarian VC panelist and his protest was only a murmured one.


Yes indeed, the times they are a-changing – or depressing – or both.


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Chapter 7: Eternal Sunshine of the Spotless Mind – Innovate, Act & Share


Luckily before I got to the FSA on August 21st, I spent the morning at sunny Sun Microsystems nearby where everything was goodness, lightness, eco-responsible, open source, and humus on pita bread, served up with rock music and slim, trim Silicon Valley techno-execs – specifically Sun CIO, Bob Worrall, Sun VP of Eco Responsibility, Dave Douglas, and Sun CTO, John Fowler – all speaking to the art of Doing More with Less: less energy, fewer dollars, and smaller spaces.


Sun invited a range of customers, press, and local community leaders onto their Santa Clara campus to celebrate the ribbon cutting of their new, highly energy-efficient datacenter – a facility that would make both Arnold Schwarzenegger and Al Gore jump for joy, and one of three such earth-friendly facilities Sun has opened so far this year. The other two are located in Blackwater, U.K. and Bangalore, India.


Between the opening hour’s presentation in the main auditorium – complete with testimonials from Silicon Valley Power – and the chance to stand out in the sunshine to see the actual ribbon being cut in front of the datacenter, it was as uplifting and downright appealing an event as I’ve been to in a long, long time. Kudos to Sun for marrying corporate profit motives with eco-citizenry, and packaging it up in a way that makes others think it’s really possible. They even apologized for dispensing bottled water to the attendees – how politically correct is that?


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-- Peggy Aycinena, EDACafe.com Contributing Editor.


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