August 06, 2007
It’s the Network Stupid, the Network-On-Chip, that is.
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Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
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It is all over the map because the designs typically take 18 months. The design cycle can be as long as 18 months. But most people do two projects or more. It is somewhere around 9 months on average. You hit a few situations where if you are exactly at the right time when the project is starting and at the tail end of the definition phase before the architecture is locked in, you can have sales cycles as short as 4 or 5 months. About 9 months would be normal.

If you are selling a new and faster simulator, it should be easy and straightforward to do a benchmark. Wouldn’t this type of product require a redesign of some sort to benchmark?

Because of the decisions we have made in terms of being able to conform to virtually all of the IP protocols, we can actually design with our automated tools a NoC instance pretty quickly that can be basically dropped in to replace a bus. We wind up with the benchmarking phase being fairly quick. The customer does not have to change anything about the chip except the interconnect. The benchmark can be challenging but it can be done reasonably quickly.

What obstacles stand in your way to capture the lion’s share of the $1 billion market you see?

The biggest obstacle right now is that some of the major companies have decided that they are not going to do this in house but the majority market has not yet decided that they are going to outsource this function. I think that this is the biggest barrier to the market bring fairly large. This particular situation has been there with the processor in the early 90s. People said that they would never outsource their processor core. Today almost no one does their processor core. Another one would be logic synthesis. All the major companies had large synthesis projects under way. Today everybody uses Synopsys or Cadence. Once a technology like the NoC gets to a point where it has
horizontal applications where multiple companies can use it virtually a standard product then you end up overwhelming the internal solution but we are kind of at that point where it is becoming obvious that the NoC will do that but the major companies have not made the decision yet.

Is that simply a not invented here syndrome or are their legitimate issues. Software programmers resisted the move to higher level languages because they felt that assembly language programs performed better. Do your tools give you a “better” design or just a design in less time?

With the NoC there are no penalties to pay. The NoC is area competitive and latency competitive with a bus for complex SoCs. You give up nothing by using a network and you actually gain a lot. As you said this song has been played several times before over and over again. The outcome is the same in the end. It will take a couple of years.

Anything to add?

We think the network-on-chip or the interconnect is the next growth area of IP. It is a strategic technology that is emerging that will allow all of the IP industry to grow because one of the big features of network-on-chip is IP reuse. It will become much easier to add, adapt, subtract and test third party and internal IPs. We think that mass adoption of this technology will be very good for the IP industry and for the EDA industry.

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Other EDA News

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-- Jack Horgan, Contributing Editor.


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