August 06, 2007
It’s the Network Stupid, the Network-On-Chip, that is.
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Jack Horgan - Contributing Editor


by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

It is all over the map because the designs typically take 18 months. The design cycle can be as long as 18 months. But most people do two projects or more. It is somewhere around 9 months on average. You hit a few situations where if you are exactly at the right time when the project is starting and at the tail end of the definition phase before the architecture is locked in, you can have sales cycles as short as 4 or 5 months. About 9 months would be normal.


If you are selling a new and faster simulator, it should be easy and straightforward to do a benchmark. Wouldn’t this type of product require a redesign of some sort to benchmark?

Because of the decisions we have made in terms of being able to conform to virtually all of the IP protocols, we can actually design with our automated tools a NoC instance pretty quickly that can be basically dropped in to replace a bus. We wind up with the benchmarking phase being fairly quick. The customer does not have to change anything about the chip except the interconnect. The benchmark can be challenging but it can be done reasonably quickly.


What obstacles stand in your way to capture the lion’s share of the $1 billion market you see?

The biggest obstacle right now is that some of the major companies have decided that they are not going to do this in house but the majority market has not yet decided that they are going to outsource this function. I think that this is the biggest barrier to the market bring fairly large. This particular situation has been there with the processor in the early 90s. People said that they would never outsource their processor core. Today almost no one does their processor core. Another one would be logic synthesis. All the major companies had large synthesis projects under way. Today everybody uses Synopsys or Cadence. Once a technology like the NoC gets to a point where it has
horizontal applications where multiple companies can use it virtually a standard product then you end up overwhelming the internal solution but we are kind of at that point where it is becoming obvious that the NoC will do that but the major companies have not made the decision yet.


Is that simply a not invented here syndrome or are their legitimate issues. Software programmers resisted the move to higher level languages because they felt that assembly language programs performed better. Do your tools give you a “better” design or just a design in less time?

With the NoC there are no penalties to pay. The NoC is area competitive and latency competitive with a bus for complex SoCs. You give up nothing by using a network and you actually gain a lot. As you said this song has been played several times before over and over again. The outcome is the same in the end. It will take a couple of years.


Anything to add?

We think the network-on-chip or the interconnect is the next growth area of IP. It is a strategic technology that is emerging that will allow all of the IP industry to grow because one of the big features of network-on-chip is IP reuse. It will become much easier to add, adapt, subtract and test third party and internal IPs. We think that mass adoption of this technology will be very good for the IP industry and for the EDA industry.


The top articles over the last two weeks as determined by the number of readers were:


Cadence Reports Q2 Revenue Up 9% Over Q2 2006 Cadence reported second quarter 2007 revenue of $391 million, an increase of 9 percent over the $359 million reported for the same period in 2006. On a GAAP basis, Cadence recognized net income of $60 million, or $0.20 per share on a diluted basis, in the second quarter of 2007, compared to $30 million, or $0.10 per share on a diluted basis, in the same period in 2006.


Atrenta Appoints Mike Gianfagna as Vice President of Marketing Gianfagna reports to Dr. Ajoy Bose, and is responsible for the company's worldwide marketing initiatives and strategic alliances. Most recently, Mr. Gianfagna was vice president of Design Business at Brion Technologies, an ASML company. Prior to that, he was president and CEO for Aprio Technologies, a venture funded design for manufacturability company. Before Aprio, Mr. Gianfagna served eSilicon Corporation, a leading custom chip provider, as
vice president of marketing. Mr. Gianfagna has also held senior executive positions at Cadence Design Systems and Zycad Corporation.


Do you like being a SMALL FISH in a big pond, or would you prefer to be a BIG FISH in a small pond It comes down to personal choice. In the case of the start-up, you need to decide if you want your contribution recognized by all, and have your input be a factor in the success of the day-to-day future of the company. Or, would you simply prefer to be a part of one group in a place of many groups


Chartered Reports Results for Second Quarter 2007 Revenues including Chartered's share of SMP were $353.0 million, down 10.3 percent from $393.7 million in the year-ago quarter, primarily due to weakness in the consumer sector, partially offset by strength in the communications and computer sectors. Sequentially, revenues were up 0.2 percent compared to $323.8 million in first quarter 2007. Revenues including Chartered's share of SMP were up 2.2 percent from $345.3 million in first quarter 2007, primarily
due to strength in the communications and consumer sectors, significantly offset by weakness in the computer sector.


Penny Herscher Joins Xoomsys as Advisor
Penny is president and CEO of FirstRain, Inc., the leading provider of search-driven research applications for investment professionals. Prior to joining FirstRain Penny was chairman and CEO of Simplex Solutions, which she grew from a few engineers in 1996 to a profitable software company, an IPO in 2001 and the sale of the company to Cadence Design Systems in 2002. Penny then worked with Cadence as chief marketing officer and general manager of a software division. Before Simplex, she was an executive at Synopsys for eight years and started her career as an R&D engineer with Texas Instruments and then Daisy Systems. Penny serves on the
boards of the Anita Borg Institute and California Community Partners for Youth and holds a B.A. with honors in mathematics from Cambridge University in England.


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-- Jack Horgan, EDACafe.com Contributing Editor.


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