July 30, 2007
Nanotechnology – Science vs. Engineering
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Cadence Design Systems also announced that Toumaz Technology used Cadence’s Virtuoso AMS Designer Simulator for mixed-signal simulation in the verification of a recently developed product, Sensium, “an ultra low power sensor interface and transceiver platform for a wide range of healthcare and lifestyle management applications.”

Meanwhile, Toumaz Technology announced its Sensium Platform Integrated Development Environment Resource (SPIDER). The company says the development kit includes two Sensium hardware development boards for the sensor transmitter and the receiver base station, respectively, Keil 8051 compiler, and JTAG debugger.

Cadence announced, as well, that CES Design Services, the Technology Center for Chip Design at Siemens IT Solutions and Services PSE, is using Cadence assertion-based verification IP (ABVIP). The companies say the technology center serves both the Siemens group and non-Siemens customers.

Finally. Cadence announced a “silicon validation collaboration” with Jazz Semiconductor working on Cadence’s RF Design Methodology and AMS Methodology kits. Per the Press Release: Jazz supports design and methodology kits based on the Cadence Virtuoso’ custom design platform … Jazz's Analog-Mixed-Signal Process Design Kits (JAMS PDKs), based on its 0.18-micron Silicon Germanium (SiGe) process (SBC18), now support the Cadence technology and usage models … with the intent to extend the collaboration to the Jazz SiGe 0.13-micron process family.”

Calypto Design Systems announced Doug Aitelli has been named Vice President of Worldwide Sales. Aitelli has 20+ years’ EDA sales and sales management experience, most recently as Director of Global Accounts at Magma. Previously, he held various sales and sales management roles at Synopsys, Quickturn, and Racal-Redac/HHB Systems.

Carbon Design Systems
announced a program to offer customers of Tenison Design Automation’s VTOC products an easy migration path to Carbon’s family of model generation solutions. Per the Press Release: “The Tenison Migration Program is a limited-time offer that includes free use of Carbon’s tools, custom integration software, and tailored services to speed the migration in exchange for signing on with Carbon. The program runs now through October 31, 2007.” “Our migration program is designed to give Tenison’s customers peace of mind that they will have a fully supported solution to continuously meet their design needs,” remarks Scott
Seaton, Carbon’s vice president of sales. “We’ve previously been successful in migrating multiple Tenison customer’s to Carbon in a couple weeks each.”

Cimmetry Systems, a subsidiary of Agile Software, recently acquired by Oracle, announced AutoVue v.19.2, which “solidifies Cimmetry's presence in the electronics and high-tech market with new EDA centric product offerings to address the specific requirements of PCB design and contract manufacturing.” Does that put Oracle in the EDA market?

Dolphin Integration announced a high-resolution measurement ADC, that the company says is for SoCs for low frequency sensor applications and MEMS: “SensADC-16.02 covers optimally the needs of measurement applications with stringent requirements in terms of noise management: blood pressure sensors or weight scales for medical markets, as well as all kinds of high-resolution wireless sensors.”

EEMBC, The Embedded Microprocessor Benchmark Consortium, announced that Cypress Semiconductor has joined EEMBC as a member of the consortium’s workgroup focused on developing multi-core and system-level benchmarks for automotive and industrial applications.

EMA Design Automation announced it now offers SymXpert from Perception Software: “As large-pin-count components are more frequently used in PCB designs, the creation of schematic symbols for new parts has become increasingly time consuming and error prone. … SymXpert automates the symbol creation process by eliminating manual data entry and simplifying pin data verification [with these] features: intelligent content extraction, data validation, rule-based graphics and pin arrangement, and template driven generation.”

FSA announced that Dwight Decker, non-executive chairman at Conexant Systems, has been named FSA Chairman. Sanjay Jha, who has been in the role for three years, will assume Decker’s role as vice chairman. The rotation in leadership roles is effective immediately. Decker has served on FSA’s Board of Directors for six years and has been FSA vice chairman since 2004. Prior to Conexant, Decker was senior vice president of Rockwell International and president of Rockwell Semiconductor Systems.

announced it has expanded its 3D packaging research program to include system design methodologies. Per the Press Release: “Both the technology and design sub-programs will be based on actual system requirements and closely coupled …IMEC also added a design technology sub-program in which system architectures will be revised. By involving other companies such as e.g. fabless companies and EDA companies, IMEC aims to develop 3D architecture methodologies enabling 3D optimization across heterogeneous technologies … In the future, IMEC intends to extend its 3D system technology program with a 3D IC program which will investigate wafer stacking for interconnects at the
IC local interconnect level.”

In related news, Amkor Technology , and IMEC announced a 2-year collaboration agreement “o develop cost-effective, 3D integration technology based on wafer-level processing techniques.”

Meanwhile, IMEC also announced progress on high-index 193-nanometer immersion lithography, double-patterning schemes for 193-nanometer water-based immersion lithography and extreme UV (EUV) lithography. Luc Van den hove, Executive Vice President and COO at IMEC, is quoted: "Over the last year, we've made significant progress in the three litho approaches we are investigating within our advanced lithography program. Driven by the needs to quickly develop 32-nanometer processes for memory applications and based on the promising results, we are quite confident that double patterning will be taken up as an intermediate solution for 32nm half pitch before a single exposure solution
is ready for production.”

Innovative Silicon (ISi)) announced it has joined the Cadence OpenChoice IP Program, program “designed to ease the process of integrating IP such as ISi's Z-RAM into SoC designs.”

Jetway Security Micro, a security products company based in China and Elliptic have signed a license for Elliptic’s asymmetric security engines. The companies say this will “permit Jetway to better serve the emerging Asian and world markets for security incorporating high performance public key algorithms. The two companies have also agreed to collaborate on a long term basis to tailor the engines to the precise needs of the target markets and applications specified by Jetway.”

Kilopass Technology announced new XPM (Extra Permanent Memory) IP for 90-nanometer general purpose and low-power designs: “With the availability of the XPM-90G and XPM-90LP families, Kilopass [is] the first memory IP supplier to announce availability of a high density NVM technology on both general purpose and low power 90-nanometer advanced geometries.”

Knowlent Corp
. announced its Opal TBE test bench development and simulation control environment, which the company says supports all circuit simulation technologies from Synopsys. Per the Press Release: “Opal TBE will provide Synopsys users with a graphical user interface for analysis, characterization and verification of complex analog/custom blocks used in SOC designs implemented in the latest nanometer silicon technologies … Synopsys' analog and mixed-signal design customers have the advantage of a complete test bench development and simulation control environment launching simulations and post processing simulation results in a structured spec-driven

Lightspeed Logic announced new Reconfigurable Logic IP for 65- and 45-nanometer process nodes. The company says, “Because of the regularity provided by the tiling structure and the full knowledge of the immediate neighborhood of the tile, Lightspeed Logic, in partnership with its customers, can fully deploy OPC/RET technologies without facing the typical computing limitations associated with standard cell structures … Both lithography-related variability and stress-related variability are substantially reduced and the timing modeling does not need to accommodate overly pessimistic guardbanding.”

Magma Design Automation announced that Toshiba has adopted Magma's FineSim Pro and FineSim SPICE circuit simulation products, and is using the tools on “its most aggressive designs to achieve superior performance and accuracy.”

MathStar, Inc. announced that Nuvation, an electronic design services company, has joined the Certified Design Center (CDC) program. The companies say, “Members of MathStar's CDC program have been extensively trained to provide professional services to designers who are migrating to MathStar's Arrix family of field programmable object arrays (FPOAs).”

Mentor Graphics announced a collaboration with the RV-VLSI Design Center in Bangalore. Per the Press Release: “Under the auspices of its Higher Education Program, Mentor Graphics will provide the Center with leading-edge design tools for classroom instruction and academic research, by donating a complete suite of EDA tools. This donation, worth over $20 million, will enable students to gain proficiency in VLSI design and other emerging nanotechnology challenges such as design for manufacturability.”

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-- Peggy Aycinena, EDACafe.com Contributing Editor.


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