July 16, 2007
DAC 2007 Part 2: Monday Tuesday Thursday Wednesday
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

eSilicon Corp. announced a new ARM processor-based peripheral subsystem architecture. Per the Press Release: “The new subsystem reduces time-to-market for ARM Powered SoC solutions by providing developers with several industry-proven, off-the-shelf system technologies, enabling them to focus on their application-specific, value-added functions.”

Interra Systems announced “the integration and introduction” of Jaguar as a VHDL front-end to several products from OneSpin Solutions, including OneSpin’s 360 Module Verifier and 360 EC Equivalence Checkers. Peter Feist, President and CEO of OneSpin, is quoted: "We provide advanced formal verification solutions that put very specific requirements on the front-end technology … Interra's portfolio of front-end technology and Beacon test-suites for recent EDA standards, such as System Verilog RTL, SVA and PSL, and their very responsive support, saves us development time and ensures full compliance to the standards.”

Jetway Security Micro,
a security products company based in China, and Elliptic, recently ranked as the fastest growing supplier of security semiconductor IP by Gartner Research, have signed a license agreement for Elliptic's asymmetric security engines.

Per the Press Release: “The license will permit Jetway to better serve the emerging Asian and world markets for security systems requiring high performance public key algorithms. The two companies have also agreed to collaborate on a long-term basis to tailor the engines to the evolving needs of the target markets and applications specified by Jetway. Jetway Security Micro is a subsidiary of Jetway Security Information Company Ltd. which has been in business for 20 years with offices in Wuhan, Beijing and Shanghai China. The company has shipped security solutions for government and commercial applications in China and is now in an aggressive growth phase to capture more business,
not only within China but also in export markets around the world.” An interesting story.

Kilopass Technology
announced a collaboration with TSMC to develop Kilopass’ XPM NVM one-time programmable IP. The companies say XPM has been qualified on TSMC’s 0.13-micron CMOS logic process technology.

MOSIS announced availability of IBM’s 0.25 micron SiGe BiCMOS 6WL technology. The companies say the process is particularly well suited to “high-performance analog chip design for consumer wireless applications, has 5 metal layers, and supports metal-insulator-metal capacitors … Design kits that encompass IBM’s design rules, process specs, SPICE parameters, and cell libraries are available.”

Nascentric announced AuSIM MT, which the company describes as a multithreaded version of its simulator, under development for almost 2 years and based on 10 patents – 5 granted and 5 pending. Per the Press Release: “AuSIM MT was built from the ground up to automatically handle the partitioning and execution of the simulation across multiple processors … Nascentric supports the product for both AMD and Intel multi-core architectures.”

Novas Software announced the company’s roadmap for “the continuing evolution of its debug automation platform for large digital ICs and SoCs. The Novas platform unifies the languages, abstractions, and tools needed to cut in half the time it takes to understand and debug design behavior starting from system-level specification through silicon implementation. Novas' latest advancements are expected to deliver three-to-ten times more performance and capacity across the entire platform, and fuel adoption of SystemVerilog-driven verification methodologies with more automated debug solutions.”

“Performance initiatives are focused on enabling fast, fine-grained access to critical portions of big designs and new incremental, on-demand approaches that accelerate automated analysis and tracing capabilities. Novas is also building on its comprehensive SystemVerilog infrastructure with enhanced SystemVerilog Assertion (SVA) debug solutions and source code debug support for SystemVerilog Testbench (SVTB) descriptions. These capabilities are being rolled out with quarterly releases of Novas' Verdi Automated Debug System starting this month.”

OCP-IP (The Open Core Protocol International Partnership) announced support of Cadence's Assertion Based Verification IP (ABVIP) for the development and verification of the OCP protocol. Per the Press Release: “Cadence's ABVIP is used for interface monitoring in simulation, as well as exhaustive formal analysis of OCP implementation including compliance. OCP-IP is taking important steps to alleviate these design challenges by supporting the ABVIP from Cadence.” Good news.

Optimal Corp. announced IC package thermal analysis for TSMC's Reference Flow 8.0, which is targeted at 45-nanometer designs and includes statistical timing analysis for intra-die variation, automated DFM hot-spot fixing, and new dynamic low-power design methodologies.

Samsung Electronics announced
that “over the past year” it has introduced 6+ technological advancements that extend battery life in notebooks, MP3 players, digital cameras, video camcorders, multimedia phones and cellular handsets. Per the Press Release: “These design improvements are part of a concentrated effort by the company to move to more energy-efficient chip and display designs, utilizing nano-scale technology breakthroughs, new sensor technology and advanced manufacturing techniques.” Undoubtedly their pals in EDA had a hand in all of this success.

Silicon Canvas announced that PixArt Imaging selected Silicon Canvas’ Laker L3 as the standard full custom layout tool for its image sensor IC designs, and image-processing algorithm IC designs. Per the Press Release: “The selection of Laker represents an important milestone in PixArt's on-going efforts to improve overall design productivity.”

SoftJin announced that Blaze DFM is now a customer. The companies say that SoftJin tools used by Blaze include the Bi-directional OpenAccess to OASIS Translator and custom verification package for validation of software modules in Blaze's products.

SynaptiCAD released version 12 of its WaveFormer Pro and DataSheet Pro timing diagram editing and waveform translation products. The company says the new version includes 12+ new features, including an improved “timing analysis engine, timing diagram documentation capabilities, and waveform translation support.”

Synopsys announced Teradici Corp. achieved “first-time silicon success utilizing Synopsys' Galaxy Design Platform products, Discovery Verification Platform products, DesignWare IP, and Synopsys Professional Services on their first multi-million-gate SoC.” Also good news.

Tektronix announced it is using Sequence Design products in the Tektronix design flow and has “reduced design closure times by preventing time-consuming iterations between separate timing, SI, power analysis and optimization tools.” Good news, as well.

Virtutech announced that IBM used Virtutech’s Simics across a team of hundreds of developers to speed the development lifecycle of IBM’s POWER6 platform.


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-- Peggy Aycinena, EDACafe.com Contributing Editor.


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