July 16, 2007
DAC 2007 Part 2: Monday Tuesday Thursday Wednesday
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Off the wires
Acacia Research Corp announced that its Disc Link Corp. subsidiary has signed a license agreement with Altera Corp. covering patents relating to portable storage devices with links.
Agilent Technologies announced an update to the Agilent 3GPP LTE Wireless Library, which the company says “works within the ADS environment using the Agilent Ptolemy simulator to streamline the design and verification process. The library provides preconfigured simulation setups with signal sources for downlink and uplink, along with transmitter analyses such as spectrum, complementary cumulative distribution function (CCDF) and waveform measurements.”
Altera Corp. and eCosCentric Ltd. announced the eCosPro RTOS for Altera's Nios II embedded processor, the world's most versatile soft-core processor. Per the Press Release: “Altera Nios II processor customers now have access to a complete eCosPro solution consisting of the run-time system, complementary host tools, and certified third-party applications. eCosCentric will also develop, maintain and make available to Altera customers, its eCosPro Starter and Developer's Kits for the Nios II processor.”
Ansoft Corp. announced a “strategic partnership” with ZTE Corp. The companies say that ZTE engineers are using Ansoft’s signal and power integrity analysis software to predict radiated emissions and induced interference from PCBs and examine multiple PCBs within a cabinet to determine trends in system-level emissions.
Ansoft also announced its SIwave v3.5 full-wave electromagnetic field simulator, which the company says is optimized for signal-integrity, power-integrity, and electromagnetic interference (EMI) analysis of high-speed PCBs and IC packages. The company says this release includes: “a fast finite-element-based DC solver optimized for extraction of power rail geometry in complex low-voltage/high-current PCB and package designs, [and] access to voltage drop and current flow information through all layout elements (vias, bond wires, sources, resistors, inductors, etc.) in tabular format.”
ARTiSAN Software Tools announced that BAE Systems Integrated System Technologies is using ARTiSAN Studio for implementation of its OMG SysML-based systems engineering processes.
Atrenta announced that Patrizia Owen has been named CFO. Owen has 15 years’ experience working for pre-IPO and early-stage companies. Previously, she has served as CFO at DigitalPersona, inOvate Communications Group, and Beatnik, Inc. She has also worked in various capacities at I/Pro, Engage, CMGI, Compression Labs, VTel, Amgen and HP. Her experience spans multiple mergers, acquisitions, and IPOs. Owen has an MBA from the University of British Columbia and a BA in Economics from the University of Western Ontario.
Cadence Design Systems announced it has acquired Invarium, a San Jose-based developer of advanced lithography-modeling and pattern-synthesis technology. The companies say that Invarium's expertise is in “the development of pattern-synthesis technologies that enable superior photomask design and process optimization, encompassing the entire manufacturing-process flow from mask making to lithography and etch Invarium's pattern synthesis capabilities enable superior pattern resolution and faster yield ramp for designs targeted to 45-nanometer-and-below process technologies.”
Cadence Design Systems announced that Cadence SiP (system-in-package) technology is now integrated with the company’s Virtuoso and Encounter products. Per the Press Release: “Cadence [now] enables designers to converge diverse IC and package-assembly technologies into highly integrated products [Cadence SiP] supports the new OpenAccess-based Virtuoso platform for an RF-module design and circuit-simulation-based flow. It integrates a new post-layout parasitic extraction and back annotation flow into automatically maintained circuit-simulation test benches.”
The news was endorsed by STMicroelectronics, and includes these additional details: “The new SiP digital flow includes logical co-design connectivity and authoring support, as part of the System Connectivity Manager. This isolates the front-end designer from physical-only changes, such as pin swap association ... Other enhancements to this release, for both the RF and digital flows, include autobond for rapid wirebond padring evaluation, object-action and action-object use models, improved SI model-extraction accuracy for designs without reference planes, 3D die stack object swapping, extended manufacturing signoff rules, and capabilities for manufacturing accurate wirebond
profiles and parasitic models.”
Cadence announced, as well, that Ikanos Communications is using the Incisive Palladium accelerator/emulator series for system-level verification needs.
Cadence also announced an “advanced design flow to improve manufacturability and yield for 65 nanometer designs” has been developed by STARC, based on Cadence products. The organizations say they have been collaborating for 15+ months to provide STARC member companies with these new DFM capabilities.
Finally, Cadence has been very busy because it has also announced its Logic Design Team Solution, which the Press Release says, “offers a new design with physical approach that [automatically delivers] an accurate physical description of the design into the logic design stage Logic design teams now can automatically design and synthesize with real physical floorplan data, virtually eliminating disparities between logical and physical timing views The Cadence Logic Design Team Solution [replaces] traditional statistical wireload models with real physical timing information. The RTL-to-gate transformation and optimization process is driven by a proprietary Physical Layout Estimation (PLE) algorithm in [Cadence’s] Encounter RTL Compiler [Then, Cadence’s] First Encounter silicon virtual prototyping capability is incorporated into the synthesis cockpit to quickly obtain the most accurate view of physical interconnect timing. The combination of physical layout estimation algorithms and embedded silicon virtual prototyping technologies creates a comprehensive interconnect modeling strategy that spans from RTL-to-gate level and accurately models both long and short wires, [eliminating] disparities between logical and physical timing views, virtually eradicating schedule-killing, big-loop iterations and the need to over-margin
timing at the cost of power.”
CAST, Inc. announced a new version of its JPEG 2000 encoder core. The JPEGK2-E core was developed by CAST partner, Alma Technologies, and per the Press Release, is “faster, requires no external processing, adds significant features, and is customizable and highly scalable [This] new version provides high-quality compression of still or video images using the JPEG 2000 standard (ISO/IEC 15444-1) [It] improves processing and makes it significantly easier to integrate JPEG 2000 in ASIC- or FPGA-based systems. [It includes]: nearly twice the processing speed of the previous version, with some of the fastest processing rates available – over 100
MSamples/sec for FPGAs and over 200 MSamples/sec for ASICs; a new rate control capability, by which image quality is maximized while maintaining a constant post-compression bit rate that satisfies a system’s transmission and decoding requirements; expanded support for arbitrary large images, now handling frame sizes up to 4096 by 4096 pixels without tiling; and full hardware handling of both Tier-1 and Tier-2 JPEG 2000 encoding, eliminating the need to do Tier-2 encoding in software running on an additional processor.”
Ciranova announced version 4.1 of its PyCell Studio is now available on multiple platforms, including Microsoft Windows. Per the Press Release: “For the first time, developers will be able to author PCells using Windows-based environments, and then deploy them on another platform, such as Linux or Solaris. A single PyCell library will work on any platform, regardless of which platform was used to create it.”
CMC Microsystems announced Ian McWalter is the new President and CEO. McWalter has 30+ years’ experience in the semiconductor and electronics industries, and 15 years’ experience on the CMC Board of Directors where he served as Chairman from 1993 to 2005. Previously, he has served as CEO of Toumaz Technology and President/CEO of Gennum Corp. McWalter also held management positions with Bell Northern Research (now Nortel Networks). He has a PhD in EE and a BSc in physics from the Imperial College of Science and Technology in London.
Denali Software announced that Beceem Communications incorporated Denali’s Databahn DDR memory controller into Beceem’s “first commercially available terminal chipset for the latest Mobile WiMAX standard.” The companies say that “Databahn DDR controller IP enabled Beceem engineers to achieve optimal system-level performance for its DRAM systems in the design of the 802.16-2005 mobile wireless BCS200 chipset.”
edacentrum announced it’s edaTrend 2007 Conference Reports, covering both DATE 2007 and DAC 2007. Per the Press Release: “edacentrum’s edaTrend’ reports focus on essential industry, technology and business trends highlighted and discussed in conference keynote addresses, panel discussions, and some special sessions, as well as issues raised on the exhibition floor. They also contain source and reference information, and a short written evaluation with ratings for each session.” The reports cost 250 euros, plus tax, and comes in a paperback version perfect for reading on the beach or a PDF version more suitable for the office over coffee
and a doughnut.
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-- Peggy Aycinena, EDACafe.com Contributing Editor.
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