July 16, 2007
DAC 2007 Part 2: Monday Tuesday Thursday Wednesday
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Wednesday morning, noon, and night
Wednesday, June 6th, was my last day in San Diego. I was running out of steam, out of attention span, and growing sick of running on caffeine. However, I didn’t have to moderate any panels on Wednesday, so it was the one day at DAC I was honestly looking forward to. And, surprisingly enough, the best part of the day was the 10 minutes I spent at Starbucks in the Convention Center. I got into a deep, albeit too-short, conversation with an EDA executive who let me in on a big secret about DAC, and EDA.
Per the exec, the convention was somewhat under attended this year for one solid reason. The semiconductor guys in Asia were not there in great numbers, or at least not compared to previous years. And that’s because the semiconductor guys in Asia are struggling with both business issues and design issues, and the two issues are linked. Again per this exec, the EDA vendors are not stepping up to help their customers in Asia as effectively as they might because the EDA vendors continue to maintain that they can and should be calling the shots as far as which tools to develop, and which markets to pursue. It seemed a confusing picture. Why would the EDA vendors not be fully tuned to
what their customers need and want? I don’t know. Do you?
Meanwhile, Wednesday was Auto Day at DAC. I went to two Pavilion Panels and a technical session/panel discussion, and learned the same thing several times over. Cars are cool, cars are everywhere, and cars are all about Semiconductors on Board. In fact, cars are just mobile platforms, so move over Detroit because cars are no longer about drive trains They’re about embedded systems and the only question that remains is: How soon will drivers catch on, sit back, and leave the driving to the systems on board?
I actually learned one other thing about cars on DAC Wednesday. I learned that Carnegie Mellon seems to have the lion’s share of the funding when it comes to academia partnering with industry and/or government to pursue advanced research. Perhaps not a fair conclusion, and I’m sure many universities would protest, but CMU was everywhere on Auto Day at DAC on Wednesday.
At lunchtime on Wednesday, I attended a large meeting of IPL – stands for Interoperable PCell Libraries – an alliance of EDA companies who are collaborating to “create and promote” standards for open-source interoperable PCell libraries that support the OpenAccess database from Si2. The companies include AWR, Ciranova, Silicon Canvas, Silicon Navigator, Synopsys, Magma, and Virage Logic.
So far, they’ve produced “a high-quality proof-of-concept library using a generic 0.13 micron process [which] demonstrates that the IPL mechanism works.” Sigh.
This is a really big, complex, and contentious issue and you can bet you’ll be hearing lots more about in the coming months (and years). The take-away I gleaned from my visit to the luncheon? “You can have PCells with no SKIL required.” That’s a pun. If you don’t get it, go to the IPL website and see if you can figure it out.
Over the course of Wednesday at DAC, I also met with executives from various companies including Denali, VaST, IC Manage, Algotronix, SynCira, CoWare, VeriEZ Solutions, and Synopsys.
In truth, I found all of these conversations to be enriching. The executives and folks who are at the helm of the EDA companies, big and small, are fascinating folks. They are criticized for so many things – for being marketeers, for attempting to control the market, for putting spin on bad news, or worse, putting spin on good news, for overstating their worth, financial or otherwise, and, of course, for producing imperfect tools. But at the end of the day, the buck stops with these guys. And so does my DAC report.
As I flew out of San Diego Wednesday evening and glanced back at a city aglow in the setting sun, it was hard not to contemplate the leadership in the industry. It’s no secret that the executives of all of the EDA companies are, appropriately and constantly, looking down at their bottom line and over their shoulders to their investors, stockholders, and Boards of Directors. An EDA executive’s life is full of stress and concerns – everything from keeping the lights on to deciding, yet again, whether or not to buy into a booth at DAC next year. These are tough decisions and never easy. Sure, it’s simple enough for me to say, “Of course you should be
coming back to DAC!” But that answer may not be so clear to these managers.
So let me put it a different way. If electronic design automation is tough and needs constant innovation, and if innovation is about interacting with customers, competing and/or partnering with other vendors, hearing from and/or funding academics and their students, and being part of an industry-wide conversation – where better to do all of this than at a conference where all of the parties involved are in attendance?
From my perspective that conference looks like the Design Automation Conference. And from multiple conversations I was privy to in San Diego, I think many would agree with me. But only time will tell.
The sun has set on the 44th DAC in San Diego, but preparations are already underway for the 45th DAC, scheduled for next year in June. For now, I look forward to seeing all of you in Anaheim in 2008 and hope you all will be there as the beat goes on in EDA. The story of this industry, and this conference, is a great one – albeit complex and often difficult to decipher – and I believe there are many more chapters to be told before it comes to an end.
In the weeks after DAC
Although the industry usually issues a joint sigh of exhaustion after DAC, the news continues to come pouring out of the companies (see below). These last several weeks, Cadence has been particularly active with announcements of various technology initiatives and/or releases including tools for system-in-package design, and tools to bring physical design data upstream to the logic designers in a more painless/appealing way. Cadence capped off recent news items by acquiring a company in the DFM space, Invarium, an enterprise that provides tools for lithography modeling and so forth.
Meanwhile – speaking alphabetically – Agilent (wireless library update), Altera (embedded processor), Ansoft (EMF simulator), CAST (JPEG encoder core), Ciranova (PCell authoring tool), eSilicon (peripheral subsystem architecture), Interra (VHDL front-end), Nascentric (multi-thread simulator), and Novas (unified debug roadmap) also all made interesting technology announcements in recent weeks. Don’t any of these people know how to spell S-u-m-m-e-r V-a-c-a-t-i-o-n?
Call for papers
Ansoft Corp. announced its First-Pass System Success application workshops, taking place September 12th through November 15th in Asia, North America and Europe. Papers can be submitted up to August 31, 2007 via the company’s website, and should address such topics as IC design and verification, signal and power integrity simulation, RF, microwave and antenna design, and packaging and PCB design.
DATE 2007 is calling for papers in the areas of design methods, tools, algorithms and languages, design, test methods and tools, and embedded systems software. The deadline is September 9, 2007 for the March 2008 conference in Munch (March 10-14).
ISQED 2007 is calling for papers, as well, in the areas of manufacturing processes and devices, design, and EDA tools. The deadline is September 30, 2007 for the March 2008 conference in San Jose (March 17-19).
You can find the full EDACafe event calendar here.
To read more news, click here.
-- Peggy Aycinena, EDACafe.com Contributing Editor.
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