June 18, 2007
DAC 2007 – Perceptions of Primacy in Pleasantville
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Reactive NanoTechnologies developed and manufactures NanoFoil, and announced $14.3 million in a Series C round of financing led by Siemens Venture Capital and existing investor, Sevin Rosen Funds. Per the Press Release: “NanoFoil, a reactive nano-layered material that precisely controls the instantaneous release of heat energy for joining and reaction initiation applications, enables rapid joining of similar and dissimilar materials without incurring thermal damage.”

Sagantec announced a DFM solution for correcting lithography hot spots found in physical IC designs developed in collaboration with Mentor Graphics. The new DFM flow uses Mentor Graphics' Calibre LFD to analyze the design layout and detect lithography hot spots. Sagantec's DFM-Fix tool uses the Calibre LFD analysis results to correct hot spots and optimize the overall layout, which is then verified by Calibre LFD. Per the Press Release: “This solution addresses a wide range of lithography-related issues and works with multiple design styles, including memory, custom and digital, and multiple levels of design, including library, IP core, block and full-chip.”

Sequence Design announced that CoolTime now addresses PGA (power gating analysis) and SSN (simultaneous switching noise) through automated analysis capabilities that the company says “enable faster, more accurate power signoff … CoolTime offers a fast ‘what-if’ PGA capability that enables users to rapidly determine switch turn-on sequence to control peak rush current and minimize wake-up time.”

Sequence Design also announced CoolTime-PGA will be added to the STARC (Japanese Semiconductor Technology Academic Research Center) advanced design flow, STARCAD-CEL.

Sequence Design also announced William Ruby has been named Vice President for Product and Applications Engineering. Prior to joining Sequence, Ruby was a senior exec at Golden Gate Technology. In 20+ years, Ruby has also worked with Intel, Cadence, Synopsys, and Siemens. He has an MBA from San Jose State, a BA in physics from U.C. Berkeley, and an MSEE from USC.

Si2, The Silicon Integration Initiative's Open Modeling Coalition, has finalized the Si2 Effective Current Source Modeling (ECSM) Statistical Extensions specification draft.
Per the Press Release: “The new specification will be released, after approval, as an Si2 standard after a 60-day patent exclusionary period completes. On release, the statistical version of ECSM will become available to the broad electronics industry, both users and EDA vendors alike, regardless of Si2 membership.”

Silicon Canvas
announced what the company calls the “first DFM-compliant technology files offering built-in DFM targeting TSMC advanced process technologies. In a new use model pioneered in Silicon Canvas' Laker custom IC design tools, when design for manufacturing and ‘recommended’ rules are included in the Laker tech files, the user can choose from a number of recommended rule sets, and Laker's built-in DFM features will automatically generate, or guide the user to generate, layout incorporating a more manufacturable and DFM-compliant configuration. These built-in Laker DFM features require no scripting and support advanced design requirements such as multiple
rule sets; conditional rules; recommended rules; discrete gate spacing; minimum area rules; routing jog avoidance; via-doubling; and more.”

Simberian announced an agreement with Mentor Graphics to partner in the OpenDoor program. The companies say, “Through this agreement, Simberian’s 3D full-wave field solver for multi-layered circuits, Simbeor can output electromagnetic models of transmission lines and via-holes directly to HyperLynx and Eldo formats for accurate system level design of high-speed serial PCB and packaging interconnects.”

Sonics announced availability of MemMax RD, which the company describes as “a new version of Sonics' MemMax Memory scheduler solution that contains a seamless interface and pre-verified configuration and initialization settings optimized for the Synopsys DesignWare DDR2 SDRAM Protocol Controller IP.”

Synopsys and TSMC announced Synopsys support for TSMC's Reference Flow 8.0 and 45-nanometer process technologies. Synopsys says it is supporting Reference Flow 8.0 in its Galaxy design platform, Discovery verification platform, and DFM products.

Synopsys also announced that Al Castino and John Schwarz have joined the company’s Board of Directors, which now includes 7 independent members. Castino will serve on Synopsys' Audit Committee; Schwarz will serve on the company's Compensation Committee. Both new directors will also serve on the company's Nominating and Corporate Governance Committee. Castino is Senior Vice President and CFO at Autodesk; Schwarz is CEO of Business Objects.

also announced its VMM Catalyst Program to further accelerate widespread adoption and support of the industry-leading VMM verification methodology for SystemVerilog. Per the Press Release: “The VMM Catalyst Program is open to EDA vendors, silicon and verification IP companies, and training and service providers to benefit mutual customers by advancing tool interoperability and the availability of IP and services using the VMM methodology. Industry support from more than 50 firms and widespread customer adoption has established the VMM methodology as the de facto standard methodology for verifying complex electronic chips. The VMM Catalyst program helps meet the growing
demand for productive and interoperable verification flows taking advantage of the full power of SystemVerilog.”

Synopsys also announced that a four winners of Synopsys' seventh annual Tenzing Norgay Interoperability Achievement Award for their “vital, initial support of a single standard for low-power design and verification. Texas Instruments, Nokia, Mentor Graphics, and Magma Design Automation together with Synopsys demonstrated strong support from the outset for an open, fast and inclusive standard to enable an interoperable low-power design and verification solution. The resulting Unified Power Format (UPF) is the newest Accellera standard approved in February 2007.”

Synopsys and Hitachi High-Technologies Corp. announced the companies have developed a “seamless link between Hitachi High-Tech's DesignGauge design data measuring system and Synopsys' Proteus optical proximity correction (OPC) solution.”

announced a definitive agreement to acquire all of the outstanding shares of HARDI Electronics AB, a company that develops of off-the-shelf ASIC prototyping boards (see news item above). The deal is said to involve $24.2 million in cash. Per the Press Release: “HARDI's ASIC Prototyping System (HAPS) is used worldwide by industry-leading companies such as Broadcom, Conexant, LG, LSI Logic, Marvell, Matsushita, Nokia, NXP, Philips, Samsung, Sharp, Sony, and TI … The ASIC prototyping market is one the fastest growing segments of the EDA industry, and this acquisition makes Synplicity the leader in this part of the ASIC verification market.”

Synplicity also announced the Confirma platform, which the company describes as “a next generation, high-performance verification solution that dramatically improves the traditional ASIC and ASSP verification process … The Confirma platform includes Synplicity's Certify tool, the industry standard for multi-FPGA partitioning and implementation; as well as the company's recently introduced Identify Pro software with TotalRecall technology providing full visibility into the design under test; and, the HAPS FPGA-based prototyping hardware, the most flexible prototyping boards on the market today.”

Teseda Corp. announced an exclusive hardware licensing agreement with INTER ACTION Corp. and two new executives. John Molloy is now leader of the North American and European sales teams, and Ralph Sanchez is now leader of the engineering team. As a result of this agreement, INTER ACTION will be the worldwide hardware manufacturing and logistics partner for Teseda's diagnostic test offering.

Virage Logic
announced the appointment of Pete Rodriguez as Chief Marketing Officer and Kamalesh Ruparel as Vice President of Silicon Technology. Rodriguez has 23+ years’ semiconductor industry engineering, sales and senior management experience. He currently is a director for EXAR and previously was president, CEO and a director of Xpedion Design Systems, acquired by Agilent. Prior to Xpedion, he held senior management positions at Escalade, until its acquisition by Mentor Graphics. He held senior positions at LSI Logic, and various positions at Aerojet Electronics, Teledyne Microwave, and Siliconix. Rodriguez has a BS in Chemical Engineering from CalTech, an MSEE
from Cal Poly Pomona, and an MBA from Pepperdine University. Ruparel has 22+ years’ IC ecosystem experience and joins the company from Anchor Bay Technologies, where he served as vice president of engineering. Previously he was at Cisco Systems, Apple Computer, Vertex Semiconductor, and Texas Instruments. Ruparel has a BSEE from the U.T. Austin and an MS in CS from the Southern Methodist University in Dallas.

The VSI Alliance (VSIA) announced the public release of Quality IP (QIP) Metric version 4.0, which the organization says includes the verification IP (VIP) extension. Cadence, Denali, EDA Centrum, Freescale, LSI, Mentor Graphics, Synopsys, and UMC all say they participated in the development of the VIP extension. Importantly, the QIP Metric version 4.0 is available for free on the VSIA website.

You can find the full EDACafe event calendar here.

To read more news, click here.

-- Peggy Aycinena, EDACafe.com Contributing Editor.


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