June 18, 2007
DAC 2007 – Perceptions of Primacy in Pleasantville
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

The Common Platform technology alliance
– IBM, Chartered Semiconductor Manufacturing and Samsung Electronics – announced availability of DFM technology models, data files and design kits from “leading” EDA and DFM companies, supporting Common Platform technology at 45 nanometers. Per the Press Release: “This is the second node, following 65 nanometers, where the alliance partners have driven comprehensive DFM solutions, which marry technology and tool support from leading EDA and DFM suppliers with manufacturing data and models from the Common Platform technology foundries to help ensure the success of chip designs at this advanced technology node across
all three manufacturers' fabs.”

CoWare, AXE, and BeatCraft announced that the AXE axLinux and BeatCraft JAKAR Media Framework have been integrated with the CoWare Virtual Platform. Per the Press Release: “The integration demonstrates the value of virtual platforms for software development and extends CoWare's ecosystem for the delivery of software-driven architecture development solutions. It also enables customers to leverage both AXE and BeatCraft expertise for virtual platform-based software development.”

Cree, Inc. and Applied Wave Research (AWR) announced a process design kit (PDK) supporting Cree's GaN process. Per the Press Release: “The kit enables monolithic microwave integrated circuit (MMIC) designers to use Cree's GaN MMIC process within AWR's Microwave Office software environment.”

Denali Software and Mentor Graphics announced availability of Denali's PureSpec verification IP products integrated with Mentor's AVM (Advanced Verification Methodology) SystemVerilog environment. The companies say the “integration is a result of a collaborative effort between Mentor and Denali to address the rapid migration towards SystemVerilog in their respective customer bases.”

Dust Networks and Kilopass Technology announced that Kilopass XPM memory is being used in Dust Networks’ embedded wireless sensor networking products. Per the Press Release: “Dust Networks’ SmartMesh-XD Mote-on-Chip (MoC) products employ the XPM non-volatile storage for analog tuning and secure storage of proprietary firmware … Kilopass’ XPM Memory is embedded in Dust’s SoC-based products, and uses a standard CMOS logic process with no extra steps. It is easily programmed in the factory and is virtually impossible to reverse engineer.” That’s good news.

EMA Design Automation
announced TimingDesigner 9.0, which the company says includes design kits with assembled diagrams and libraries for commonly used parts and interface protocol standards, and program modifications to accommodate the latest features of the newest operating systems. Per the Press Release: “Each kit consists of all documented timing protocols associated with one or more design components, and are assembled for easy importation into TimingDesigner's Manager Window allowing quick assembly of any timing project.” Manny Marcano, President and CEO of EMA, is quoted in that same Press Release: "Since acquiring TimingDesigner a short time ago, our design
team has been working diligently to add value to benefit our customers.”

EVE announced an addition to its ZeBu hardware-assisted verification family. Per the Press Release: “Using the MMB with ZeBu-UF, the SoC under verification can be connected to real peripherals or to test equipment to mimic a complete and scalable SoC verification environment tuned to perform all hardware and software validation tasks of any MultiMedia/Portable SoC. The MMB can be further expanded via daughter modules to accommodate additional interfaces such as HDMI, Still Digital Camera and Video Digital Analog converter.”

HARDI Electronics announced its HapsTrak compatible SerDes (high-speed serial transceiver) daughter board, which contains an ASIC SerDes evaluation chip from LSI Logic. The SerDes daughter board will be compatible with all previous and future generations of HAPS (HARDI ASIC Prototyping System) motherboards.

KLA-Tencor announced LithoWare, which the company describes as “a new Linux-based product enabling semiconductor circuit designers to dramatically reduce the time and cost to develop RET and OPC processes. LithoWare is a lithography optimization tool based on the industry-standard PROLITH models that reduces time-to-production by allowing customers to co-optimize the RET and the process conditions simultaneously, while minimizing calibration data collection.”

Magma Design Automation and TSMC announced that Magma's Blast and Talus, Quartz SSTA statistical analysis, Quartz DFM and SiliconSmart DFM tools are included in TSMC Reference Flow 8.0.

The MathWorks
announced Simulink Design Verifier, which the company says “generates tests and proves design properties for Simulink and Stateflow models using the Prover Plug-In from Prover Technology. Developers of embedded systems, especially complex or safety-critical systems, can now automatically obtain test cases to satisfy industry-standard metrics, such as modified condition/decision coverage (MC/DC), while uncovering design errors earlier in the development process when they are significantly less expensive to fix ... Simulink Design Verifier augments simulation with new verification and validation technology based on formal methods that significantly reduces the need to
hand-code tests for establishing complete model coverage and verifying requirements.”

Mentor Graphics and Chartered Semiconductor Manufacturing announced a partnership that the companies say will offer a series of mixed-signal Technology Design Kits (TDKs) supporting 65- and 90-nanometer process technology available from Chartered. Per the Press Release: “The kits have been validated and are available now for use with Mentor Graphics ICstudio design platform … The new TDKs enable the entire analog mixed-signal IC design flow to be tailored for customers using Common Platform technology processes.”

Mentor Graphics also announced that the Common Platform Technology alliance – IBM, Chartered and Samsung – have qualified the Calibre suite of DFM tools. Per the Press Release: “The collaboration between Mentor Graphics and the Common Platform foundries provides an integrated DFM solution to address both random and systematic yield limiters for 65-nanometer and 45-nanometer processes …The new DFM flow uses Mentor's Calibre YieldAnalyzer to perform critical area analysis (CAA) on all base and interconnect layers of a design.”

Mentor Graphics, covering all its bases, also announced along with TSMC that Mentor's DFM and DFT tools have been incorporated into TSMC Reference Flow 8.0. The new Reference Flow 8.0 features Mentor tools for critical area analysis and reduction, chemical-mechanical polishing (CMP) analysis and layer planarity control using smart fill algorithms, litho-friendly design, process variability aware analysis, and DFT flows based on Mentor Graphics’ Calibre and TestKompress “solutions.”

Mentor Graphics
also announced it has acquired Sierra Design Automation, a provider of high-performance place and route solutions. The company was purchased for $90 million, payable 50 percent in cash and 50 percent in Mentor Graphics common stock. Pravin Madhani, Sierra President and CEO, is quoted: "At 65 and 45 nanometers, discontinuities such as process variation, design size, low power and DFM are creating a major disruption in physical design. The merger with Mentor enables us to deliver a powerful design-to-fab flow that addresses these discontinuities in a comprehensive fashion." Wally Rhines, Mentor Chairman and CEO, is also quoted: "Our leading-edge customers are
telling us that they need a design-to-fab flow capable of handling dozens of process corners and multiple modes, all while addressing manufacturability challenges to achieve manufacturing closure of their designs. Mentor's and Sierra's leadership in these areas make us a natural fit. The acquisition of Sierra expands Mentor's leadership in DFM, and provides the integration that customers need between physical design, and back-end verification and yield-enhancement." ST Microelectronics provided endorsement of the acquisition in the Press Release.

MIPS Technologies announced that Cadence Design Systems, Magma Design Automation, Mentor Graphics, and Synopsys will team with the company to provide EDA software and tools support for its MIPS32 74K core family. Last month, MIPS Technologies announced its next-generation 32-bit processor family, which the company describes as “the industry's first fully synthesizable processors to surpass 1 GHz operating frequencies in TSMC 65-nanometer process technology.”

MunEDA announced a licensing agreement with Faraday Technology regarding MunEDA's DFM-DFY tool family, WiCkeD. Per the Press Release: “By choosing MunEDA's leading-edge technology to improve design performance and yield, Faraday is well armed for the new challenges in the nano era.”

Pro Design and videantis GmbH announced the integration of real-time H.264/AVC baseline profile encoder on a CHIPit Platinum prototyping system.

Pyxis Technology announced Phil Bishop has been named President and CEO. Bishop has 25+ years’ experience in high tech. Previously, he was President and CEO of Celoxica, where he took the company public. He has served as a non-executive chairman of the board for Silistix, has worked for Mentor Graphics as vice president and general manager of worldwide consulting, and held engineering and management roles at Motorola, Freescale, and Boeing. Bishop has a BSEE and a BSCE from the University of Michigan, and an MBA from Duke.

You can find the full EDACafe event calendar here.

To read more news, click here.

-- Peggy Aycinena, EDACafe.com Contributing Editor.


Review Article Be the first to review this article


Featured Video
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Acquiring Mentor: Four Good Ideas, One Great
More Editorial  
Manager, Field Applications Engineering for Real Intent at Sunnyvale, CA
SENIOR ASIC Design Engineer for TiBit Communications at Petaluma, CA
Sr. staff ASIC Design Engineer -2433 for Microchip at San Jose, CA
Upcoming Events
DeviceWerx - 2016 at Green Valley Ranch Casino & Resort Las Vegas NV - Nov 3 - 4, 2016
2016 International Conference On Computer Aided Design at Doubletree Hotel Austin TX - Nov 7 - 10, 2016
ICCAD 2016, Nov 7-10, 2016 at Doubletree Hotel in Austin, TX at Doubletree Hotel Austin TX - Nov 7 - 10, 2016
Electric&Hybrid Aerospace Technology Symposium 2016 at Conference Centre East. Koelnmesse (East Entrance) Messeplatz 1 Cologne Germany - Nov 9 - 10, 2016
S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy