June 18, 2007
DAC 2007 – Perceptions of Primacy in Pleasantville
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Then Tuesday dawned and we never heard about it again.
Cadence stock sagged back a bit, and by Wednesday at DAC, people forgot Monday had ever happened. The few who could remember 2 days back were frequently cynical, openly calling the whole thing a publicity grab and a move by “unnamed sources” to wrest control of the PR machine that runs in overdrive at DAC.
By the start of the following week, the Blackstone Group was, ironically, front-page news across the nation, but not because of Cadence. It seems Blackstone is set for an IPO in just a few weeks, and has been forced to reveal details of its executive compensation including $400 million in 2006 for CEO Stephen Schwarzman and $213 million in 2006 for Founder/COO Peter Peterson.
Also, per Associated Press reports, the Chinese government controls 9.7 percent of the company by way of a $3 billion investment in Blackstone Group in May 2007. Maybe they were anticipating the Blackstone transaction with respect to Cadence and wanted to get in on the action? In any case, now 9 days later it’s tough to find any news related to DAC Monday’s “hot” story about Cadence, Blackstone Group, and KKR.
The real thing
DAC. The implications from this story are complex.
First, it would appear the guys at Reed lost out on this particular scoop – it was a CMP story from start to finish. So much for perceptions of primacy at Reed. CMP won this one outright.
Second, it would appear that Wally Rhines and his team at Mentor are tired of playing a cheerful, but distant 3rd to Cadence and Synopsys when it comes to having something sorta kinda like a complete design flow to offer their customers. Mentor is in the game.
Third, it would appear the folks who went on record for my EDA Weekly article on DFM in May missed the boat when they failed to mention Sierra Design as a significant player in the DFM space. Even Sierra’s Director of Marketing, Sudhakar Jilla, named Mentor, Synopsys, and Clear Shape in that article, but not Sierra Design. Or, is it the case that Sierra Design actually only provides a part of the DFM solution, but a part that Mentor thought it faster to buy than develop and hence the acquisition?
Finally, when it comes to perceptions of primacy in Pleasantville, or EDA for that matter, one should be careful of jumping to conclusions. As Terri Fiez emphasized at the close of her keynote at the Women’s Workshop in offering career advice to the upwardly mobile in her audience – when it comes to leadership, try everything that you’ve learned through experience or training, but realize that sometimes, “You just have to be the alpha male!”
Mike Fister may have been hailed as the Alpha Male of EDA on June 4th, but by June 11th, I think Wally Rhines had better claim to the title. Wally and Richard Goering, that is.
Next time: DAC Tuesday & Wednesday
News from in and around DAC
steps ahead of today's industry, anticipating the direction of tomorrow's wireless technologies and products," sayeth Jim McGillivary, vice president and general manager of Agilent's EEsof EDA division.
Aldec announced a new Verilog linting engine, ALINT, that the company says complies with the second edition of the STARC "RTL Design Style Guide." ALINT supports rules that cover various levels of RTL design cycle, and “provides flexible configuration features that allow companies to control implementation of corporate design guidelines.”
Ansoft announced HFSS v11, which the company says includes new technology that delivers “greater accuracy, capacity, and performance” than earlier versions, including higher-order hierarchical basis functions combined with an iterative solver that uses smaller meshes and “more efficient solutions for large multi-wavelength structures HFSS [simulates] very complex models two to five times faster using half of the memory compared to previous versions.”
AXIOM Design Automation announced it has endorsed the Unified Power Format for power-aware designs and fully supports UPF in its MPSim Verification Solution. Per the Press Release: “Now design engineers using Magma's IC implementation system and the verification engineer using the MPSim verification environment can use the same low-power description.”
Berkeley Design Automation announced that Luminary Micro has chosen Berkeley Design’s Analog FastSPICE circuit simulator for full-circuit verification and verification of complex blocks “at 5x to 10x the speeds previously available to Luminary with full SPICE accuracy.”
Berkeley Design also announced that Newport Media has adopted the company's Analog FastSPICE circuit simulator.
President and CEO of Phase Forward. Previously, he was Senior Vice President at Viewlogic Systems. Tasker has an MBA from U.T. Arlington, and a BS in Statistics and Economics from the University of Bombay.
Cadence Design Systems and TSMC announced that Cadence is providing “key capabilities” to TSMC Reference Flow 8.0. Per the Press Release: “The Cadence contribution within TSMC Reference Flow 8.0 is based on several new capabilities in the Cadence Encounter digital IC design platform and the Cadence Logic Design Team Solution.” Lucky TSMC.
Cadence also announced, in conjunction with TSMC, availability of the Cadence QRC Extraction tool for parasitic extraction for TSMC's 45-nanometer technology.
Cadence also announced that Realtek Semiconductor Corp. has completed an “aggressive low-power design” using Cadence’s Logic Design Team Solution. Interestingly, per the Press Release, “Realtek is a leading Taiwan IC design house offering a comprehensive range of communication network, computer peripheral, and multimedia ICs.”
Certess announced it has selected Verific Design Automation's HDL Component Software to serve as the front-end for Certess’ newly released Certitude functional qualification tool.
ClariPhy Communications and Helic S.A. announced an engineering collaboration over the past 12 months, which has been instrumental in the first-pass success of ClariPhy's single-chip, 10GBASE-LRM, mixed-signal CMOS transceiver. Per the Press Release: “ClariPhy selected Helic's EDA tool, VeloceRF, after diligent evaluation.” One would certainly hope so.
CLK Design Automation announced that has linked its Amber Analyzer incremental static timing and signal integrity analysis tool to Verific Design Automation's HDL Component Software. The companies say that Verific's Verilog Netlist Parser serves as the front-end to the Amber Analyzer and “runs smoothly on 64-bit machines.”
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-- Peggy Aycinena, EDACafe.com Contributing Editor.
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