June 18, 2007
DAC 2007 – Perceptions of Primacy in Pleasantville
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| by Peggy Aycinena - Contributing Editor
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It’s always difficult to decipher the Design Automation Conference, particularly when it’s set in San Diego – California’s version of Pleasantville. The sun is ubiquitous there, the people clean-cut and courteous, the water tidy and blue. One could come away from a DAC set in such a venue and believe that a) DAC is dull or dying, or b) EDA is dull or dying. However, if you came away with such a conclusion you’d be a) wrong or b) dead wrong.
DAC is neither dull nor dead, and neither is EDA. On the contrary, both DAC and EDA continue to be populated by the most intelligent, competitive, bickering, jealously-jockeying-for-position, alpha-male population anywhere within the semiconductor design and supply chain. A fact that makes a DAC set in Pleasantville one of the more interesting to participate in and/or observe.
Don’t be fooled for a minute just because the 44th DAC seemed quiet that the people within the EDA industry are courteous, tidy, or blue. They’re not. In fact, they’re discourteous, messy, and come in every color except blue. And this is the way things should be in an industry that needs disruptive thinking, rebellious behavior, and inventive irreverence to keep progressing forward, ever forward, into that ITRS roadmap that stretches off into the distance of the next decade, century, or millennium.
Sunday morning, noon, and night
Sunday, June 3rd, dawned before dawn in San Diego with the start of the 10th annual Rock n’ Roll Marathon that wound its way through 26.2 miles of city’s highways and byways. In that huge gathering of 20,000 runners, San Diego showed itself to be welcoming and awash in live music every mile or so along the course. It was a great moment for the city, but not so great for those hurrying to the San Diego Convention Center to attend DAC tutorials or construct booths on the Exhibition Show Floor. Streets were closed all over town which, when added to San Diego’s propensity for one-way streets and road construction projects, made it a pretty tough go for those traversing
the city by car.
The DAC tutorials and booth construction persevered, however. I attended snippets of two tutorials in the Convention Center on Sunday afternoon – a keynote from ArtisanSW CEO Jeremy Goulding which was part of the UML for SoC Design Workshop (with an audience of 45+ people), and a panel discussion which was part of the Low Power Coalition (LPC) Workshop (also with an audience of 45+).
Goulding invoked Geoffrey Moore
and Henry Ford
, and said early adopters are not always winners, and a proliferation of vendors is always needed for technology innovation. Goulding also noted that Gartner tracks 68 different “hype-cycle” technologies, but not UML. He concluded that since UML is neither a trendy technology nor remarkably successful to date, it’s destined to eventual greatness through a proliferation of vendors and mid-to-late cycle adoption. He said UML will handle increased design complexity and higher levels of abstraction once good standards for the language are put in place. His talk was well received, and UML Workshop organizers noted that
for the first time this year representatives from the Big Guys in EDA were all in attendance. I predict you’ll be hearing much more from the UML space in coming years.
The panel discussion at the Si2-sponsored LPC Workshop next door was not quite as inspiring. Clearly there’s a problem brewing in the EDA community between UPF (Accellera’s United Power Format, championed by Synopsys, Mentor, and Magma) and CPF (Si2’s Common Power Format, championed by LPC and Cadence). A pox on the houses of all of the players who have let this situation develop, but as noted earlier, EDA is nothing if not about Alpha Companies, and nobody that I spoke to at DAC believes the players involved in this controversy are going to stand down anytime soon. That’s sad news for the many smaller players in EDA who find themselves having to support both UPF and
CPF in their tool offerings. Hence, it was with some skepticism that I listened to the companies on the LPC panel – AMD, ARM, ArchPro, Atrenta, Cadence, Calypto, LSI Logic, NXP, and Sequence.
Standing at the back of the room, Si2 CEO Steve Schulz
tried to bring coherence to a scattered conversation, and asked the panelists to talk about a possible CPF roadmap. Comments from panelists included: “CPF was powerful enough to describe a helluva lot of stuff more than 2 years ago, but is it powerful enough to do everything we want to do today? Not yet, because the industry has some work to do.” “There is a danger of moving too fast. We could put everything including the kitchen sink into the format and find there are no tools to support it.” “[Things will progress] once you have multiple proof points, more than just the Cadence flow we’ve got
Representatives of all of the Big Guys in EDA, folks from both sides of the low power format controversy, were very visibly present in the audience and as Si2’s Sumit DasGupta concluded the panel and the workshop – “LPC at Si2 is a customer-driven group formed to address issues related to low-power design flows. CPF 1.0 is available for free from Si2 and serves as the starting foundation for current and future work in low power. Join LPC and drive the industry forward.” – the applause was not deafening.
The UFP faction were up next, down the hall at their Design & Verification of Low Power ICs Workshop
from 4 PM to 7 PM. For those interested in the Compare & Contrast Game, attending the CPF and UPF workshops in quick succession was a compelling opportunity. But the EDAC Annual Cocktail Confab and Executive Reception
started at 5 PM in the Marriott next door to the Convention Center, and given a choice between UPF and an open bar, it seemed many voted with their feet. Hundreds showed up for the EDAC event, but as things turned out, they might have been better off opting for the UPF event still underway in the Convention Center. Because, although great thought and good
intentions undoubtedly went into assembling the panel discussion which was at the center of the 5-to-7 o’clock EDAC event, the conversation between the 11 men on stage seemed scripted and dull. Come on – 11 people? That’s not an event, that’s Death by Disaggregation.
The panel – billed as two panels for the price of one – was moderated by EN’s Ed Sperling
and EDN’s Ron Wilson
, both from Reed and both seated at the center of the stage. The right half of the stage was populated with EDA users including Qualcomm, eSilicon, National Semiconductor, and Broadcom. The left hand of the stage was populated by EDA suppliers and enigmatically included ARM and TSMC (these are EDA guys?) along with Analog Bits, Synopsys, and Magma. Sperling promised that the 75-minute panel would “break down walls” between vendors and users. Following are only some of the many words of wisdom from those 75 minutes that I typed into
my laptop between sips of white wine. Try to guess if the comments come from the right side of the stage or the left, and try to see if any walls are tumbling down.
The scaling era is finished. When are you going to enable [design] with tools that do everything from architecture down to silicon implementation? We’ve been dabbling in the ESL space, [but] John Cooley says few engineers are actually using it. The concept resonating now is virtual platforms. Predictability relies on modeling and extraction. The model needs to know how the silicon will behave. We need to know the impact of tradeoffs at the top of the design process. ESL? I’m not even sure what that is. Any amount of reuse is a good thing, but how can you re-architect a design? As we go forward, things are going to get harder. The IP industry is so fragmented, even if
you’re using IP you’re not really using IP. Changing from technology to technology makes it hard to do reuse. Integrating IP is really hard, because there are no standard EDA tools that help you integrate. The only IP that doesn’t cause problems is obsolete IP. Reuse is a moot point in analog. If you’re doing something that’s never been done before, that’s not IP, that’s design services. Let’s quote Ronald Reagan: “Trust but verify.” Verification and IP are all linked. Verification has become a huge problem. Not only are designs getting bigger, they’re
poorly architected and impossible to verify. There’s hope behind SystemVerilog. It moves up in abstraction, is more object oriented, multi vendor, with less lines of code, and can create designs that are more regular and verifiable. The way to get better silicon is to use logic BIST. I’m enjoying being on this panel because of the sheer joy of beating up on the EDA vendors.
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-- Peggy Aycinena, EDACafe.com Contributing Editor.
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