June 04, 2007
DAC's Dynamic Duo: Marie & Pat Pistilli
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Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Mentor also announced that
UMC has expanded its support for the Calibre nm Platform with Calibre YieldAnalyzer for major design flows for its 90-nanometer and 65-nanometer processes. Not surprisingly, then, Mentor and UMC announced a new reference flow for analog mixed-signal (AMS) SoC designs. The companies say the flow includes an integrated environment for design capture, data management, and verification.

Mentor also announced that
Fujitsu Ltd. will use Mentor’s Calibre LFD to “enhance their Design for Manufacturing (DFM) capabilities in the manufacturing of semiconductors both for internal product development and for external fabless customers.”

Mentor, as well, announced it has validated Calibre LFD (litho-friendly design) results in silicon on 65-nanometer process technology. Per the Press Release: “A joint paper by Infineon Technologies and Chartered Semiconductor Manufacturing documents the positive results that can be achieved by implementing a lithographic process verification flow using Mentor Graphics’ Calibre LFD.”

Mentor reminds readers they are also an IP vendor by announcing its new Serial ATA (SATA) physical layer (PHY) IP core, targeted for the TSMC 130-nanometer Low Voltage Oxide (LVOD) process, that Mentor says “provides a completely integrated solution for both SATA host and device applications running at either 1.5Gbps or 3.0Gbps speeds. The SATA PHY has one of the industry’s smallest footprints based on its efficient analog circuitry design.”

OneSpin Solutions announced it has joined
Accellera and will serve on the Unified Coverage Interoperability Standard (UCIS) Technical Subcommittee.

OneSpin Solutions also announced a new sales and field applications engineering office in Yokohama, Japan, OneSpin Solutions Japan KK.

OneSpin Solutions, as well, announced what the company calls “the industry’s first complete solution that simultaneously verifies multiple configurable IP components at once. This new capability, which ensures error-free functioning of each individual configuration, comes standard with the company’s flagship 360 MV solution.”

Open-Silicon, Inc. announced it acquired the intellectual property assets of
Zenasis Technology. The Press Release says, the acquisition “expands Open-Silicon’s Science of ASICs initiative.” Naveed Sherwani, president and CEO of Open-Silicon, is quoted in that same Press Release: “By incorporating this new technology, we will be able to optimize our customer’s designs for performance, power, and area, and improve their time to market, which will allow them to differentiate themselves in the market. This is exactly what the ASIC market needs.”

Optimal Corp. announced expanded capabilities for its PakSi-E quasi-static EM analysis software for IC package, system-in-package, and PCB design. Per the Press Release: “PakSi-E’s performance has been improved by approximately 3X across a range of design with no sacrifice in accuracy. Other improvements include a newly integrated CAD front-end, an overhauled and modernized GUI, and Linux and 64-bit support.” Dave DeMaria, Optimal CEO, is quoted in that same Press Release: “These new capabilities offer a major step forward to a unified analysis environment for signal, power, and thermal integrity.”

ProDesign announced the CHIPit V5 series of ASIC Prototyping platforms that the company says are based on
Xilinx Virtex 5 FPGA technology and an “integrated set of tools with strong debugging capabilities.” Platform enhancements include: a scalable product family from 1 up to 21 FPGAs, which can handle up to 28 M ASIC gates; user-guided flow for design implementation and system handling; integrated software to spread the design over multiple FPGAs, and support for various verification modes including co-simulation, transaction-based co-modeling, and in-circuit emulation up to 200 Mhz.

ProDesign also announced a various new and enhanced versions of its CHIPit product line: CHIPit Copper Edition V5, for “flexible and affordable prototyping system with newest Virtex 5 technology”; CHIPit Iridium Edition V5, with “ more features and prototyping system with newest Virtex 5 technology; and CHIPit Platinum V5, with high capacity and high-end prototyping system with newest Virtex 5 technology.” Lucky Xilinx.

Samsung announced development of a mobile phone memory card that the company says provides “record storage capacity.” The product is an 8GB microSD memory card, “a size optimal for storing large multimedia files in mobile phones” and is capable of storing 2,000 MP3 music files, 4,000 digital photos, or five DVD movies (10 hours). The memory cards are a quarter the size of an SD card and are backward compatible with SD cards using an extender, which allows multimedia files downloaded by mobile phones to be displayed on other media.”

Sierra Design Automation announced “innovations” to Sierra’s place & route platform “to address 45-nanometer design including interconnect resistance variation, complex DRCs and yield.” The innovations include: “FalconGR global routing technology that assigns layers dynamically during P&R and is embedded within engines such as placement, CTS, and detailed routing; Multi-Corner CTS technology to minimizes intra- and inter-corner skew and insertion delays in a single run.; and enhancements to the global, track and detailed routing engines to model 45-nanometer design rules and recommended DFM rules throughout the routing

Sequence Design announced a collaborative effort with
Mentor Graphics that the companies say “has resulted in an integrated ESL power exploration flow … With this flow, designers can automatically generate and analyze multiple ESL-based implementations to find the optimum balance of performance, area, and power.” The companies also say this project is a result of Sequence's membership in the Mentor Graphics' OpenDoor partnership program.

Sequence Design also announced upgrades for its Columbus parasitic extractors. New features include statistically-accurate corners for 65-nanometers interconnects, Speedview-AMS for full-custom voltage-drop and EM analysis, and fast-rail extraction for LVS flows. Sequence also announced that
Sanyo Semiconductor has signed a long-term agreement to use Columbus-AMS.

Sequence Design announced, as well, the PowerTheater-Explorer option for the company’s RTL power analysis engine. Per the Press Release : “The option adds power visualization and debug capabilities, a SmartSource Viewer to determine hot spots in the design, and to visualize, debug and interactively determine ways to reduce power.”

Sigrity announced OrbitIO Planner, which the company says is “the first single tool for dynamic, multi-domain planning across ICs, packages and PCBs … The only solution to provide a full physical view of all interconnect domains of a system and allow real-time exploration and optimization of the IO interface … Once the optimized IO plan has been established, the data is pushed back to the originating sources in their native formats …This breakthrough solution is made possible by a unified data model that merges the IC, package, and PCB data into a single data representation.”

Silicon Navigator Corp. announced three new software engines for its RDE Framework (RDE) – SKILL compatible PCell Editor, RTL Power Analysis, and Schematic Editor. Per the Press Release: “The engines augment RDE's existing engines for RTL processing, static timing analysis, layout editing, mask processing, data translation, and graphic display. CEO
George Janac is quoted: "Our new engines are in answer to CAD developers' requests for broader flow coverage and better OpenAccess integration so Internal CAD solutions can cover new and unmet chip design needs. Our engines represent a new EDA licensing paradigm of supplying component-based software that supports tool development and integration within large and small corporations,"

The RDE engines increase productivity for CAD developers and speed up CAD design tool development by allowing CAD developers to spend time on solving design problems rather than building basic functionality. Extensions facilitate the development of comprehensive EDA solutions on a unified standards-based environment

The Singapore Economic Development Board (EDB) announced an investment of $5.3 million for water fabrication training, with plans to produce 300 engineers in the specialization annually. The EDB says it is working with local universities to encourage undergraduates to take up water fabrication training. Stipends will be offered to students depending on the number of years of their specialization, and the Press Release says that all sponsored students can expect guaranteed job offers upon graduation. It also says: “There are 14 operating wafer fabrication facilities, 20 assembly and test operations and 40 IC design centers in Singapore.”

SMSC announced the Hi-Speed USB 2.0 USB251x hub controller and the USB331x ULPI transceiver families. Per the Press Release: “The new Hi-Speed USB hub controllers provide the industry’s smallest footprint connectivity options that give designers up to a 60-percent space savings compared to previously available devices. Through advancements in power and space efficiencies, the new ULPI transceivers are the most full-featured transceivers available today.”

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-- Peggy Aycinena, EDACafe.com Contributing Editor.


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